Timing Diagram and Static "1" Hazard Elimination

[@rehrucken3267]

It helped me a lot and I´m studying electronical engineering.
Cheers little fella

[@aepeessla]

FINNALY UNDERSTOOD IT! Thank you sm

[@dayyalaravi4996]

Hello mam,
Is there any need to redraw the circuit for eliminated hazard..?

[@surajbhatt5807]

Which software is this for making 📝??

[@MohanKumar-kg6bl]

Hello mam you explained well I have one doubt that is you are consider the delay due to only one not gate what about one more not gate why you don't consider that one?

[@danhan5760]

C: change.
A: no change.

[@eitoes]

Great video ma'am

[@vidhiruparelia4706]

hello, which book has this been taken from??

[@dachosen114]

Fundamentals of Logic Design, Enhanced Edition
by Roth/Kinney/John

[@kaminarinokogo6206]

Thank You so much for the wonderful explanation ! May I know the name of the Professor ?

[@oliverbeck6839]

tank,u mam, vry gd explanation (:

[@alirezamoosavian3143]

great video! thanks a lot

[@faijul-amin]

Best explanation upon this problem.many many thanks

[@xdrockstar865]

gd explanation. b8 u may take more simple circuit for this.

[@aminsakha155]

thanks a lot

[@awjalanfatimi2300]

thanks a lot ^_^

[@Aimyrocks]

Thanks

[@eunicevilar3086]

otimo!!!