Gate Delay and Timing Diagrams

[@yeiyang8698]

thanks for the explanation
It's really helpful

[@ZeroG]

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[@kinzarashid2277]

So how many gate delays does this 2-level circuit experience in total to compute F? Is it 1, since the input C had to wait at the AND gate for the other input (X) to come in from the output of the OR gate?

[@virgelhyung]

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[@israelarroyo7572]

Why wouldn’t c be high until the 15 ns ?

[@rajkulvi3622]

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[@taruntej7867]

Then what is the mean of contamination delay..

[@ashrafhussein3028]

I like the explanation

[@lacrimosa6140]

thanks for the explanation

[@sreekar0345]

Well Explained

[@bijoybasumataryy8870]

God

[@vangee_ee1234]

Sound