CMOS inverter - charging & discharging time Clock skew - adv & disadv Types of power dissipation in CMOS inverter Latch & flipflop where we use & o/p waveform Aspect Ratio of MOSFET changes parameters of MOSFET how? Order of priority of timing,power,area while designing IC 3-types of inverters and comparing their performance Recents for Static & dynamic power dissipation and dependency on Threshold voltage Power dissipation reduction? Which parameters to vary to cover power dissipation for above Vlsi design flow Setup & hold time ( why,how,for latch too) Latch using mux Puzzles Resume
Did you attend the synopsys interview..?are you selected in the interview? Which type of technical amplitude questions are there in interview can you tell me about the your interview.....
Hi, Digital Integrated Circuits by Jan M Rabaey is a standard textbook on the subject. you can refer the section "Timing Properties of Multiplexer-based Master-Slave Registers" in Chapter 7 - DESIGNING SEQUENTIAL LOGIC CIRCUITS, of Rabaey (page no. 308), to see why setup and hold time exist. You could extend similar reasoning for other circuits.
Please continue making such videos. It would help students to get a job in a good company which they were unaware of.
CMOS inverter - charging & discharging time
Clock skew - adv & disadv
Types of power dissipation in CMOS inverter
Latch & flipflop where we use & o/p waveform
Aspect Ratio of MOSFET changes parameters of MOSFET how?
Order of priority of timing,power,area while designing IC
3-types of inverters and comparing their performance
Recents for Static & dynamic power dissipation and dependency on Threshold voltage
Power dissipation reduction?
Which parameters to vary to cover power dissipation for above
Vlsi design flow
Setup & hold time ( why,how,for latch too)
Latch using mux
Puzzles
Resume
Did you attend the synopsys interview..?are you selected in the interview? Which type of technical amplitude questions are there in interview can you tell me about the your interview.....
Thank you😇 bro for sharing....
Thanks a lot very beneficial your video, can you also make a video on how to do preparation? please
Seems like you attended interview for Physical Design position
👍👍 thanks
I can't really understand the question at 4:45, Realize Adder using 2x1 mux then u said using single Adder. Can you please Explain
Thanks, bro.
Useful video bro.
Please suggest good resources to learn system verilog for design verification
Thanks Bro!
what is the academic eligibility criteria for synopsis
Nice. However it would have been good if u had given the answers too.
I wish you could also give answer
What would a CAE engineer do at Synopsys?
For softaware CS what questions are possible ?
Bro, can you give the answers for these questions? That will be helpful
thank you so much for sharing the video.can you share any topic related to STA...
Refer nptel lectures on physical design
thanks bro....
What is the difference between inverters you told
I want to join in a core company ! I am thinking to take a training program .! Can you help me by suggesting few training centres!
I am sorry, i won't be the right person to answer this.
Do a course from Cdac
Thank you
Does education gap matters during placements ?
Yes it is.
no,only domain knowledege
will you plz give the answer of these question?
Thank u so much
How to apply campus drive for synopsys 2018 bro..
Most of the big companies do post job openings on LinkedIn. You can follow the companies you like and apply via LinkedIn itself.
@@SPACE-vw4zh okiee bro..
Can you tell answers
Thanks
thanks man
Congrats.. jeff...
tq ...brother....
Hii bro I'm trying for job vlsi can you tell which resources are good to practice and reading
Maven silicon
In which city/state/country was the Synopsys office located ?
India for sure
Can u refer me a standard text book...that describes..timing issues of latches...like setup and hold time for latches...not for flip flops
Hi, Digital Integrated Circuits by Jan M Rabaey is a standard textbook on the subject. you can refer the section "Timing Properties of Multiplexer-based Master-Slave Registers" in Chapter 7 - DESIGNING SEQUENTIAL LOGIC
CIRCUITS, of Rabaey (page no. 308), to see why setup and hold time exist. You could extend similar reasoning for other circuits.
Malayali...?
bro answers plz dire need
Thank you