Very Clear Explanation................... One doubt is there that single bit is written or read in one clock period, then how you had taken whole in single period?
Your videos are really good for nice and clean concept building. I would love if u can make a video on 3rd method of synchronization that is hand shaking bw 2 clk domains
It basically means that you have an idle cycle that does nothing after a consecutive write or read. In that case, you would have to multiply the calculated time period by the number of idle cycles mentioned. Say for example, if you insert 2 idle cycles after every read (Trd =3* (1/read clock f)).
Thank You bro! I faced one question in Nvidia Placement test : FIFO depth if writing rate 45 beats/50 clock and read rate 12beats/20 clock?? when Burst size is not mentioned than how we will be able to find FIFO Depth?
You need to take the effective beats/clock for beats calc and Fifo depth = (effective beats/clock for write - effective beats/clock for read )* Burst size -> Burst size assume a number and round off the fifo depth to the nearest integer.
No, we just need a synchroniser, since receiver unit is faster than transmitter, there won't be any data "lost in translation" if we synchronise properly
For the scenario 1 FA < FB, if FA = 60 MHz and FB = 100MHz how we will send data without FIFO? For the scenario 2 FA = FB and clocks are not in Phase how can we send data without FIFO?
in scenario A, let us say that you are writing data to RAM, in this case your writing slower than reading, in other words read all data in RAM and wait for another data to be written in RAM, this doesn't need a FIFO, in scenario B if they are not in-phase either you lock their phases or synchronize both using flip flops or of course you can use FIFO, it is up to you (the designer) to decide based on the system that he/she is building
Can we calculate depth of FIFO if we don't know burst size? I mean I want read to continuous. I didn't got u r infinite depth FIFO so clearly please clarify me
If data is continously being fed to the fifo from a faster clock to a slower clock, then no fifo will ever have enough depth. Every cycle of the read, you get more than one cicle on the write, so as time goes on the fifo gets more and more filled up. At some point, if the writing side never stop, it will get completely filled up, unless the fifo had infinite depth.
Q1) draw a neat diagram of astable multivibrator using op amp explain it's work and hence derive an expression for its pulse How this pulse????Sir solve this problem Plzzz
Simply super . explained in such a way even a beginner with out any knowledge can understand.
your explanation is really simple and sweet
finest and clear explanation ever gone through!
Explaination is really good... Plz share ur knowledge... With us...
Really mind blowing explanation
Thanks for your support !!
Awesome explanation of fifo depth
Thanks Sharukh!
Very Clear Explanation................... One doubt is there that single bit is written or read in one clock period, then how you had taken whole in single period?
please explain burst size briefly ,,,,,,,,,,,and thanks!..its really finest time taken video...ever seen.
It's cool explanation, loved it!
Thanks for the clear explanation!
All I would say is this man can become brand ambassador of Sprite, siddhi baat no bakwas.
Simple and Clear👍
wonderful explaination
e
Now i figured it out !!!, Thanks :)
Much needed! Thanks for the video with great information :-)
Great video. Please make a video on much complex problems related to FIFO design
Your videos are really good for nice and clean concept building.
I would love if u can make a video on 3rd method of synchronization that is hand shaking bw 2 clk domains
the finest explanation :)
Outstanding sir
Thank you !!
Someone explain what the synchronizer circuit be in the first case where fa
very well explained
Thanks for tutoring. It is really helpful. How long does it fill the FIFO, if the FIFO depth is 20 depth?
Bahut bhadiyan
FIFO size = (fram size / TX freq) × (Tx freq - Rx freq)
= (100/200MHz)× (180MHz)
= 90
Hi can you please upload video for clock gating checks , it will helpful for us
Thank you
Explaned nicely ..... but what exactly mean you want to describe for idle cycles? that can you elaborate here?
It basically means that you have an idle cycle that does nothing after a consecutive write or read. In that case, you would have to multiply the calculated time period by the number of idle cycles mentioned.
Say for example, if you insert 2 idle cycles after every read (Trd =3* (1/read clock f)).
.
helpful!
Thank You bro! I faced one question in Nvidia Placement test : FIFO depth if writing rate 45 beats/50 clock and read rate 12beats/20 clock?? when Burst size is not mentioned than how we will be able to find FIFO Depth?
You need to take the effective beats/clock for beats calc and Fifo depth = (effective beats/clock for write - effective beats/clock for read )* Burst size -> Burst size assume a number and round off the fifo depth to the nearest integer.
which college did this exam happen in ?
@@vivekkandhagatla3096 0.9-0.6 = 0.3 beats per clock loss , but I dont know the burst rate , so 3 should have been answer in that exam maybe ?
Thank you 😊
Can you explain the same example with 3 idle cycles while reading and 1 idle cycle while writing
nice one
Nice video sir
Thanks for your appreciation !! :)
if fa>fb for single bit data crossing, what synchronizer is preferred...
That will depend on the design, use-case, etc. The video gives an overview into the problems and how to mitigate it!
@@electroTuts ok Sure and Thanks for the replay. Also could you please kindly do more video's on CDC.
make such more videos
Is fifo required even in the case of fa < fb ? . I see some fifo depth caluclations on the net in this case. can someone explain ?
No, we just need a synchroniser, since receiver unit is faster than transmitter, there won't be any data "lost in translation" if we synchronise properly
awesome
Super
For the scenario 1 FA < FB, if FA = 60 MHz and FB = 100MHz how we will send data without FIFO?
For the scenario 2 FA = FB and clocks are not in Phase how can we send data without FIFO?
in scenario A, let us say that you are writing data to RAM, in this case your writing slower than reading, in other words read all data in RAM and wait for another data to be written in RAM, this doesn't need a FIFO, in scenario B if they are not in-phase either you lock their phases or synchronize both using flip flops or of course you can use FIFO, it is up to you (the designer) to decide based on the system that he/she is building
.
Can we calculate depth of FIFO if we don't know burst size? I mean I want read to continuous. I didn't got u r infinite depth FIFO so clearly please clarify me
If data is continously being fed to the fifo from a faster clock to a slower clock, then no fifo will ever have enough depth. Every cycle of the read, you get more than one cicle on the write, so as time goes on the fifo gets more and more filled up. At some point, if the writing side never stop, it will get completely filled up, unless the fifo had infinite depth.
.
The author did not account for the worst case scenario when there is back to back burst as in 100 + 100
The depth should be 90*2 = 180
Q1) draw a neat diagram of astable multivibrator using op amp explain it's work and hence derive an expression for its pulse
How this pulse????Sir solve this problem
Plzzz
Will consider this when deciding a topic for future videos!
Sir I am started now 1 November coming on
Thanks for the clear explanation!
Glad it was helpful! :)