Electronics Interview Questions: FIFO Buffer Depth Calculation

Поділитися
Вставка
  • Опубліковано 8 лис 2024

КОМЕНТАРІ • 62

  • @ananthalavanya3143
    @ananthalavanya3143 5 років тому +4

    Simply super . explained in such a way even a beginner with out any knowledge can understand.

  • @Paul_Lanka
    @Paul_Lanka 3 роки тому

    your explanation is really simple and sweet

  • @arshiaj3751
    @arshiaj3751 3 роки тому

    finest and clear explanation ever gone through!

  • @mamathagollavilli9
    @mamathagollavilli9 4 роки тому

    Explaination is really good... Plz share ur knowledge... With us...

  • @ravindrasuryavanshi6821
    @ravindrasuryavanshi6821 5 років тому +1

    Really mind blowing explanation

  • @sharukhshaik7476
    @sharukhshaik7476 5 років тому +1

    Awesome explanation of fifo depth

  • @prashantjain1180
    @prashantjain1180 4 роки тому +1

    Very Clear Explanation................... One doubt is there that single bit is written or read in one clock period, then how you had taken whole in single period?

  • @hemchandjain2189
    @hemchandjain2189 4 роки тому

    please explain burst size briefly ,,,,,,,,,,,and thanks!..its really finest time taken video...ever seen.

  • @knowledgeunlimited
    @knowledgeunlimited 3 роки тому +1

    It's cool explanation, loved it!

  • @jaslife87
    @jaslife87 5 років тому +1

    Thanks for the clear explanation!

  • @divyamsatle6673
    @divyamsatle6673 6 місяців тому

    All I would say is this man can become brand ambassador of Sprite, siddhi baat no bakwas.

  • @praveenmamidi8726
    @praveenmamidi8726 3 роки тому

    Simple and Clear👍

  • @ujjawalagrawal5195
    @ujjawalagrawal5195 3 роки тому

    wonderful explaination
    e

  • @narenkayarmar
    @narenkayarmar 3 роки тому

    Now i figured it out !!!, Thanks :)

  • @sumukhabharadwajmohanrao853
    @sumukhabharadwajmohanrao853 3 роки тому

    Much needed! Thanks for the video with great information :-)

  • @jairamgouda
    @jairamgouda 4 роки тому

    Great video. Please make a video on much complex problems related to FIFO design

  • @Deepakkumar-tq1xv
    @Deepakkumar-tq1xv 4 роки тому

    Your videos are really good for nice and clean concept building.
    I would love if u can make a video on 3rd method of synchronization that is hand shaking bw 2 clk domains

  • @rakcea
    @rakcea 5 років тому +2

    the finest explanation :)

  • @sultanmurad2309
    @sultanmurad2309 5 років тому +1

    Outstanding sir

  • @harihara.t
    @harihara.t 3 роки тому

    Someone explain what the synchronizer circuit be in the first case where fa

  • @pavanbhandari1177
    @pavanbhandari1177 3 роки тому

    very well explained

  • @kunliu5004
    @kunliu5004 3 роки тому

    Thanks for tutoring. It is really helpful. How long does it fill the FIFO, if the FIFO depth is 20 depth?

  • @yprashant66py
    @yprashant66py 4 роки тому +2

    Bahut bhadiyan

  • @ranjanparnami
    @ranjanparnami 3 роки тому +1

    FIFO size = (fram size / TX freq) × (Tx freq - Rx freq)
    = (100/200MHz)× (180MHz)
    = 90

  • @anupalike1226
    @anupalike1226 Рік тому

    Hi can you please upload video for clock gating checks , it will helpful for us

  • @jyh4820
    @jyh4820 3 роки тому

    Thank you

  • @juntran_workbackupleppy7024
    @juntran_workbackupleppy7024 4 роки тому

    Explaned nicely ..... but what exactly mean you want to describe for idle cycles? that can you elaborate here?

    • @saiprasadszhayi
      @saiprasadszhayi 4 роки тому +1

      It basically means that you have an idle cycle that does nothing after a consecutive write or read. In that case, you would have to multiply the calculated time period by the number of idle cycles mentioned.
      Say for example, if you insert 2 idle cycles after every read (Trd =3* (1/read clock f)).

    • @alokmishra9522
      @alokmishra9522 2 роки тому

      .

  • @veeryanbhatia538
    @veeryanbhatia538 2 роки тому

    helpful!

  • @lokendrasinghlodhi718
    @lokendrasinghlodhi718 Рік тому

    Thank You bro! I faced one question in Nvidia Placement test : FIFO depth if writing rate 45 beats/50 clock and read rate 12beats/20 clock?? when Burst size is not mentioned than how we will be able to find FIFO Depth?

    • @vivekkandhagatla3096
      @vivekkandhagatla3096 Рік тому

      You need to take the effective beats/clock for beats calc and Fifo depth = (effective beats/clock for write - effective beats/clock for read )* Burst size -> Burst size assume a number and round off the fifo depth to the nearest integer.

    • @ayushagarwal69
      @ayushagarwal69 Рік тому

      which college did this exam happen in ?

    • @ayushagarwal69
      @ayushagarwal69 Рік тому

      @@vivekkandhagatla3096 0.9-0.6 = 0.3 beats per clock loss , but I dont know the burst rate , so 3 should have been answer in that exam maybe ?

  • @nitpl12
    @nitpl12 3 роки тому

    Thank you 😊

  • @maheswarreddy4394
    @maheswarreddy4394 3 роки тому

    Can you explain the same example with 3 idle cycles while reading and 1 idle cycle while writing

  • @muhammadatif5480
    @muhammadatif5480 5 років тому +1

    nice one

  • @merrygo7189
    @merrygo7189 4 роки тому

    Nice video sir

    • @electroTuts
      @electroTuts  3 роки тому

      Thanks for your appreciation !! :)

  • @Paul_Lanka
    @Paul_Lanka 3 роки тому

    if fa>fb for single bit data crossing, what synchronizer is preferred...

    • @electroTuts
      @electroTuts  3 роки тому

      That will depend on the design, use-case, etc. The video gives an overview into the problems and how to mitigate it!

    • @Paul_Lanka
      @Paul_Lanka 3 роки тому

      @@electroTuts ok Sure and Thanks for the replay. Also could you please kindly do more video's on CDC.

  • @vinayakkumthekar7752
    @vinayakkumthekar7752 5 років тому +1

    make such more videos

  • @anilkadiyala
    @anilkadiyala 4 роки тому

    Is fifo required even in the case of fa < fb ? . I see some fifo depth caluclations on the net in this case. can someone explain ?

    • @yasirpunathil7143
      @yasirpunathil7143 4 роки тому +1

      No, we just need a synchroniser, since receiver unit is faster than transmitter, there won't be any data "lost in translation" if we synchronise properly

  • @sairambingi9937
    @sairambingi9937 5 років тому

    awesome

  • @sunilkumarkp4508
    @sunilkumarkp4508 4 роки тому

    Super

  • @lizajoseph6368
    @lizajoseph6368 5 років тому +1

    For the scenario 1 FA < FB, if FA = 60 MHz and FB = 100MHz how we will send data without FIFO?
    For the scenario 2 FA = FB and clocks are not in Phase how can we send data without FIFO?

    • @ahmadalastal5303
      @ahmadalastal5303 4 роки тому +1

      in scenario A, let us say that you are writing data to RAM, in this case your writing slower than reading, in other words read all data in RAM and wait for another data to be written in RAM, this doesn't need a FIFO, in scenario B if they are not in-phase either you lock their phases or synchronize both using flip flops or of course you can use FIFO, it is up to you (the designer) to decide based on the system that he/she is building

    • @alokmishra9522
      @alokmishra9522 2 роки тому

      .

  • @pavanhegde1933
    @pavanhegde1933 5 років тому

    Can we calculate depth of FIFO if we don't know burst size? I mean I want read to continuous. I didn't got u r infinite depth FIFO so clearly please clarify me

    • @danieljimenez1989
      @danieljimenez1989 5 років тому +4

      If data is continously being fed to the fifo from a faster clock to a slower clock, then no fifo will ever have enough depth. Every cycle of the read, you get more than one cicle on the write, so as time goes on the fifo gets more and more filled up. At some point, if the writing side never stop, it will get completely filled up, unless the fifo had infinite depth.

    • @alokmishra9522
      @alokmishra9522 2 роки тому

      .

  • @amedirat
    @amedirat 2 роки тому +1

    The author did not account for the worst case scenario when there is back to back burst as in 100 + 100
    The depth should be 90*2 = 180

  • @sultanmurad2309
    @sultanmurad2309 5 років тому

    Q1) draw a neat diagram of astable multivibrator using op amp explain it's work and hence derive an expression for its pulse
    How this pulse????Sir solve this problem
    Plzzz

    • @electroTuts
      @electroTuts  5 років тому

      Will consider this when deciding a topic for future videos!

    • @sultanmurad2309
      @sultanmurad2309 5 років тому

      Sir I am started now 1 November coming on

  • @mjitglv5876
    @mjitglv5876 4 роки тому +1

    Thanks for the clear explanation!