Ah, this was asked in an AMD oncampus interview Being from ECE i was not aware of the terminology, but I managed to get to this point with the help of few directions/hints from the interviewer Thanks for clearing this out !! Guess I'll study parallel computing and computer architecture in my free time, pretty interesting !!
Mate, over 40 years ago I started out (after a bit of Fortran IV and SEL assembly language) on 'pipelined micro-code' for a 'Floating Point Array Processor Unit', which was about the size of an upright freezer, and I believe was sold by a company called "FPS Systems", and had a whole 32,768 words (each 32-bit plus some floating point stuff) of memory, and it had a five-stage instruction pipeline. It was intellectually the most fun I've ever had.
At 17:07 you mentioned that when lw follows sw, there is no data hazard. But the value to be stored will be stored at the end of mem stage. While that value will be required during ID stage. If it takes garbage value in the ID stage then it gets actual value only y forwarding. So it is ultimately a memory data hazard. Please explain.
design the following set of instructions using a 5 stage instruction pipeline. if any hazards occur, identify those hazards and redesign the pipeline for rectifying each hazard. find the number of clock cycles taken to complete the following sequence of instructions. assume all stages take one clock cycle each to complete the operation. a. add r2, r1, r0 # r2 ← r0 + r1 b. mul r4, r3, r2 #r4 ← r3 + r2 c. sub r6, r5, r4 #r6 ← r5 + r4
in the first example after reading r1 from sub instruction we could have again read r1 value from sub only for instruction AND,OR why agin read from starting ADD instruction.
You are a miracle! You explained in less than 8 minutes what no one else could explain in many, many hours! Thank you so much
Thanks Jen hope you got what u were looking for 😊
Ah, this was asked in an AMD oncampus interview
Being from ECE i was not aware of the terminology, but I managed to get to this point with the help of few directions/hints from the interviewer
Thanks for clearing this out !!
Guess I'll study parallel computing and computer architecture in my free time, pretty interesting !!
Mate, over 40 years ago I started out (after a bit of Fortran IV and SEL assembly language) on 'pipelined micro-code' for a 'Floating Point Array Processor Unit', which was about the size of an upright freezer, and I believe was sold by a company called "FPS Systems", and had a whole 32,768 words (each 32-bit plus some floating point stuff) of memory, and it had a five-stage instruction pipeline. It was intellectually the most fun I've ever had.
At 17:07 you mentioned that when lw follows sw, there is no data hazard. But the value to be stored will be stored at the end of mem stage. While that value will be required during ID stage. If it takes garbage value in the ID stage then it gets actual value only y forwarding. So it is ultimately a memory data hazard. Please explain.
design the following set of instructions using a 5 stage instruction pipeline. if any hazards occur, identify those hazards and redesign the pipeline for rectifying each hazard. find the number of clock cycles taken to complete the following sequence of instructions. assume all stages take one clock cycle each to complete the operation. a. add r2, r1, r0 # r2 ← r0 + r1 b. mul r4, r3, r2 #r4 ← r3 + r2 c. sub r6, r5, r4 #r6 ← r5 + r4
das ist super .... danke schön
I think sw syntax is wrong at 12:10. Correct me if I am wrong! Good explanation sir!
I believe the rs and rt are flipped
Confused @12:15 should it be SW R1, 4(R6) ?
Instead of SW 4(R6), R1?
Yeah I think it’s the assembly language he used. It’s different from the normal one. Confused me a bit, too.
in the first example after reading r1 from sub instruction we could have again read r1 value from sub only for instruction AND,OR
why agin read from starting ADD instruction.
Super explanation
Thank you 🙂
Thank you very much ..for all you have done !
Great explanation sir.
Thanks and welcome
great explanation sir!
the hazard is the 3rd guy learned it wrong from 2nd guy who diverged away from 1st guy
that's correct DeanRendar !!
How we to learn this concept easily
thank you so much
Thanks, Kami
👍
😂👍
@@vickys4077 vanakamuda mapla UA-cam a irunthu
Vanakam
Thank u Sir in depth Sesion
what is abbrevation of IM and DM
Instruction memory and data memory
Excellent!
Thanks Payton !! We are grateful that you appreciated our work
thank you
Sir can you solve this question?