@Mamelcrispen Not exactly, having short simple review before exam can help actually benefit you. I personally study until the very last second before the exam starts.
Load or Store are the main instructions which access memory. For inst 2 and 3, the memory is bypassed as in we don't actually read/write to memory. They both could be R-Type instructions like add and sub, where the operation is done in ALU unit, still has to go through the pipeline but as you can see it will use the line that goes under the DMem on the canonical pipeline.
Just a heads up for anyone in South Africa - do not go to UCT to study computer science. This man right here explains it so much better than my lecturers could ever
still bit unclear about 7:16, he said immediately, so is it hardcoding the result? and where the temp result stored? pipeline register? i didn't know there is addition of pipeline register to separte stages per clock, so, if there is 20 stages, there will be addition +/- 20 register in the pipeline??
"but be aware, the devil is in the detai-" *cuts to credits*
He tried to warn us
@@Not_The_Pizza_Guy lol
Excellent explanation Thank you Professor👌👏
Legend Professor. Exam in 4 hours LETSGOOOO
Exam in an hour🥲
2 hours les goooo
If you here 4 hours before an exam sorry to say bruv you failin 😢
@Mamelcrispen Not exactly, having short simple review before exam can help actually benefit you. I personally study until the very last second before the exam starts.
Ty man i Would SYD but no homo
Yo I'm fuckin crying rn 😭
what does that mean?
LMFAO
Great video. Really helped me to catch up the lectures I missed due to multiple ones overlapping
Thank you so much for this video; the comp arch professor at my university is terrible at explaining these concepts
You go to NMSU?
SAME.
Great Explanation. Found it really easy to understand.
Great video, thanks for your help.
The devil is in the what???! I NEED TO KNOW!
the devil is in the DETails!
Something is wrong why was the first sturctual hazard delayed by 1 stall it should be 3 because there are other memories users inst 2 and 3.
It was because we delay with load or store insts only
Load or Store are the main instructions which access memory. For inst 2 and 3, the memory is bypassed as in we don't actually read/write to memory. They both could be R-Type instructions like add and sub, where the operation is done in ALU unit, still has to go through the pipeline but as you can see it will use the line that goes under the DMem on the canonical pipeline.
@@melom806 thanks bro you made my concepts more clear ❤️❣️😍
confirmation. RAW data hazards cannot be solved with Forwarding/Bypased Technique.
this is such a great explanation. thank you for your effort. vielen dank
pov: You're a KIU student studying for the CA finals and you came across this gem
Thx Germany 🇩🇪 I need this for finals next week. From 🇺🇸
2:43 but the second instruction also collides with the fetch and memory doesn't it?
No since the second instruction will not be a load or store so it will not do anything during the MEM stage
@@xMaviHD Thanks! I was confused.
THANK YOU SO MUCH!!!!! YOU ARE AMAZING!!!!
Just a heads up for anyone in South Africa - do not go to UCT to study computer science. This man right here explains it so much better than my lecturers could ever
vielen Dank Herr Professor
still bit unclear about 7:16, he said immediately, so is it hardcoding the result? and where the temp result stored? pipeline register? i didn't know there is addition of pipeline register to separte stages per clock, so, if there is 20 stages, there will be addition +/- 20 register in the pipeline??
check out what he says later in the video with the connections, the value is checked during the IF operation with the MEM and WB of the previous
Professor, sorry you are wrong in structural Hazard example. Data cache is different from Instruction cache. It is not a hazard.
what would happen if there was no hazard prevention...
Everyone dies and the world burns
@@sk8terkyd326 frfr 💀
Thank you for this detailed explanation
GOOD VIDEO!!!!
Thanks much
i love u
Thank you sir...
Love u prof💙
very helpful thank you dr
Thank you very much, great explanation