A good example for the simpler explanation. But practically I think this is not the correct example. Because, simple linear counters can be easily synthesized and with a multistage counter, there is extra combo logic involved(additional 2bit Adder). A practical example where I have used multi cycle paths in my designs is, let's say the MSB, 2 bits of this counter is used in a huge combo logic that couldn't meet timing in one cycle. Then according to the behavior of these MSB bits, they change once every 4 cycles. So, functionally we have 4 cycles for the combo to settle down. So, we can set a multicycle path to 4 cycles in that case. Caution: Always have Assertions wherever Timing exceptions are used.
I have a doubt in this multistage counter...when ever overflow occurs the control logic gives the logic 1 to second register..and you are saying that the second register is having four clock cycles to increment it...but my doubt is that the second register should get immediately incremented in the next clock pulse itself ryt?? then after it has to wait for three more clock cycles to get incremented
Please go through my video on multistage counter video if you still have doubt then we can discuss. Link of multistage counter video is ua-cam.com/video/Jj8JHywYmHk/v-deo.html
@@rk-mn6mq I think you are correct…. Once the first counter overflows, in the next cycle the second counter should increase otherwise the counter values would look like 0000, 0001,0010,0011,0000,0101(probably if the second counter updates after one cycle) So, the they counter can’t take its own time… it should actually change in one cycle and it will be waiting for another load signal in next 3 cycles
It’s exceptional concept make so easy to understand
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Thank you! This is very informational.
Glad it was helpful!
A good example for the simpler explanation. But practically I think this is not the correct example. Because, simple linear counters can be easily synthesized and with a multistage counter, there is extra combo logic involved(additional 2bit Adder).
A practical example where I have used multi cycle paths in my designs is, let's say the MSB, 2 bits of this counter is used in a huge combo logic that couldn't meet timing in one cycle. Then according to the behavior of these MSB bits, they change once every 4 cycles. So, functionally we have 4 cycles for the combo to settle down. So, we can set a multicycle path to 4 cycles in that case.
Caution: Always have Assertions wherever Timing exceptions are used.
Such a good explanation. Thanks
Glad it was helpful!
Sir, Could you please upload continuation of this video ? and few more examples to understand multicycle paths
I am preparing now.
Can you please upload continuation video for next sesssion? I mean constraining multi cycle paths
Sure .. We will try as soon as possible ..
I have a doubt in this multistage counter...when ever overflow occurs the control logic gives the logic 1 to second register..and you are saying that the second register is having four clock cycles to increment it...but my doubt is that the second register should get immediately incremented in the next clock pulse itself ryt?? then after it has to wait for three more clock cycles to get incremented
Please go through my video on multistage counter video if you still have doubt then we can discuss. Link of multistage counter video is
ua-cam.com/video/Jj8JHywYmHk/v-deo.html
Ok
@@rk-mn6mq I think you are correct…. Once the first counter overflows, in the next cycle the second counter should increase otherwise the counter values would look like 0000, 0001,0010,0011,0000,0101(probably if the second counter updates after one cycle)
So, the they counter can’t take its own time… it should actually change in one cycle and it will be waiting for another load signal in next 3 cycles