Using Xray is a real cheat code. I used to maintain equipment in a machine shop/foundry and they had an Xray machine that would go through 3 inches of steel. I would occasionally Xray mechanical components that I had problems disassembling to find out what was inside.
FCC part 14 rules governing frequencies like 2.4ghz and 5.7 ghz are legal for enthusiast tinkering in the USA. You are simply not allowed to sell it as product without re-certifying. I get annoyed when people say things like this are 'illegal'. I thought you were a ham op or at least came from an RF background, you should know better.
4:16 Electrical engineer here. One small correction - those wiggles are for something called length matching. When you have a high speed group of signals that all need to get from point A to point B, they all need to be about the same length , so they get there at the same time. In this PCI-e example, they happen to be differential pairs as well, but that's not the reason why they are length matched. If you look closely at the RAM tracings you can see similar matchings there. PS: You did mention its for length matching later in the video. Sorry. i wrote the comment before i got to that point.
Thank you for the comment either way! Differential signaling / timing can be a bit confusing, especially when the majority of my work on any kind of PCBs/breadboarding is in decidedly low-speed communication :)
@@JeffGeerling 1970's PCBs with speeds in the low megahertz range are much easier to understand. I think they tag those coupled differential pairs as a "network" in the design software, keeping them uniform, straight as possible, and on the same layer. Have seen the term "MagJack" used for the integrated magnetic couplers in the RJ-45 interface housing.
Differential pairs do need to be length-matched, so it's not _wrong_ to say the squiggles are there because they're differential signals, just not the whole story.
@@hellterminator Should be length matched. When you're talking low speed you can get away with a bit of slop. Sometimes we're hand making cables, and RS-485 is very tolerant.
@@JeffGeerlingAlso regarding PCIe 3.0 being out of spec, I read in Raspberry Pi Forum a post by rpi engineer saying that clock jitter due to PLL used in the soc is the culprit
I run two Zeiss CT scanners, one can scan at sub-micron resolutions (Xradia)! Thanks for showing off this technology and the Metrology field as a whole!
I need to seriously stop just glancing at titles! I thought this said "I X-Rated My Computer" which I was like, I can respect that... Don't know that I'd make a video about it, but you know that's just me...
Wait, you didn’t know “Raspberry Pie” was going to be the next in the “American Pie” series? Because Jeff was just looking to add some Bow-chicks-wow-wow to his page…. LMAO
A lot of small VIA's in a line are often a "fence" against unwanted signals propagating through the board between layers. A sort of faraday cage. The distance between the VIA's will be slightly less than ½ wavelength of what they want to block. This requires 2 (or more) ground planes which is not uncommon.
Been doing electronics design for years now, and it's kinda crazy all the steps you gotta take to get those pci-e lanes to behave under the worst conditions, but it's also crazy just how much wiggle room you get too. I know people were using just plain bodge wire on the pi4 back when it was first discovered to have pci-e, and interestingly pci-e even has support for flipping the wires of a pair, despite them being polarized. Also, Ethernet magnetics are fascinating. My understanding is that the original intent was to deal with ground differentials, where the ground potential of a circuit could be 1000's of volts above the ground of another circuit. The PoE is a clever hack that uses the fact that you're basically scrubbing the voltage potential from the lines with the magnetics, meaning you can put whatever voltage difference you want across those lines. I know most poe uses either 24v for passive or 48v for active, but those voltages were mostly selected due to restrictions on high voltage lines in buildings (or at least that's my current understanding of it. Only source I have is friend who has been designing network circuits a decade longer than I have.). by sticking with 48v, it counts as low voltage, and in the majority of states, means it can be self-installed.
There is a lot more to it than that. 48v DC is a long standing voltage in copper Telecom circuits. It is the resting voltage provided by the LEC or Local Exchange Carrier from their switching centers to power all of the analog POTS lines around which the LEC's have to maintain service for emergency situations. That is why Switch offices are built like tanks. They have battery and generators on site to maintain power to all the analog phones connected to them. To make a POTS phone ring its sent 90v AC by the Switch. The National Electric Code or NEC that sets those standards. The National Fire Code is to prevent and reduce damage from fires. Your local building code combines those with local community needs to determine to what standards work needs to be completed to. Who can work on something is often determined by insurance but generally if you are the property owner you can do all of your own work. You should do it to standard of your local building code but it isn't required unless its commercial property. If you do it to less than the standard and its determined your work was at fault then insurance may not pay out or if its work done for someone else you may become liable for the loss. Low Voltage also inclues 110v/120v/240v AC service. 208v 3-phase AC and over 100v DC I believe are Medium Voltage but it has been a while since I looked it up.
Note that the 1500V commonly quoted for Ethernet isolation is a test voltage, *NOT* a working voltage. It's the same as the 1500V test voltage specified in most IEC standards for "basic insulation" and half that normally specified for "reinforced insulation".
You can have passive 48V POE also. Though passive POE is sort of an gray area type of thing and doesn't actually have any hard and fast rules. I've even seen people do 12V passive POE. IEEE 802.3 always has POE as active. You're right that 48V is picked because it's low enough voltage it can be self installed because it's considered low voltage in most places. The other side of that is that the higher the voltage, the more power you can deliver. That's because P=VI. Voltage drop is caused by wire resistance. You could increase wire diameter to decrease resistance, but that's not really an option for ethernet wiring. So, you really want I to be as low as possible. So, you up V to as high as you reasonably can. In either case, you'll have a DC-DC converter at the load to efficiently step that down to whatever you need.
@@ccoder4953 Operating passive PoE at those higher voltages isn't a great idea though, as it will cause additional arcing when you plug in that will wear the contacts. Standards-compliant PoE uses a lower probe voltage, and only switches up to 48V after negotiation.
It's very annoying to me that the Pi Foundation apparently went to the trouble to design a custom power management IC with Renesas but couldn't be arsed to include support for a step-down converter in it so that you could use any totally standard 27W or greater PD supply (9V3A) instead of needing the wonky custom 5V5A profile their own adapter uses, just to save a few cents. Great video, though! As an electrical engineer, no major glaring issues that I noticed. Accurate enough for a youtube video! At least one or two of the chips you mentioned as having bond wires are actually probably flip-chip and what you're seeing are the breakout traces in the package (with no flying bond wires) but it's a minor detail and I'd either need to know more about the chips in question or take a closer look at cleaner x-rays of just the bare chips to be sure.
10 місяців тому+2
THIS!!! Cannot agree more, apparently they don't care for e-waste, but only profit. Cannot imagine one logical reason for this wonky setup. Getting cost down my ass.
Just a little correction: Raspberry Pi Foundation are the nonprofit good guys behind all the OSS goodness and education support. The assholes who make proprietary solutions (like the aforementioned power profile or the FPC PCI-e connector) and shitty products (Pi4 official case that overheats the Pi even at idle, Pi 4 official case fan that barely helps but is very noisy, official display with terrible viewing angles and non-square pixels,...), who ditched their community for industry customers during the chip shortage, and who lie and play games, are the for profit company Raspberry Pi *Trading.*
@@Mr.Leeroy That's the point; the Pi is _already_ a USB PD device and uses the protocol to negotiate its profiles, they have just chosen to make it report a non-standard profile that nobody else uses so they don't have to deal with voltage conversion. Supporting this would take an inductor, a few other small support passives, and a very slightly more capable power IC (cents, like I said). Every smartphone that supports more than 15W charging managed to fit this into their much tinier mainboards, the Pi foundation just didn't consider it a priority and likely assume they are large enough to strong-arm the rest of the industry into accommodating them. The cynical take is they did it deliberately to sell more power supplies which likely have much higher margins than the Pi itself, but I don't know if I'd go quite that far myself.
@@siberx4 I was talking about proper IP block for their custom PMIC, that would be an investment in it self. If their engineers say that there was no spare PCB real estate, I believe them.. Remember, that they already had to go with not 2, not even 4, but 6 layers to cram everything into spots where everyone expect every little thing. 6+ layers production is not a joke and definitely not cents more expensive. Also their claim that wide voltage input rage would produce more heat is sound, as efficiency would drop almost certainly very dramatically with ratios Vin/Vout > 2, and buck costs are only rising at the same rate as we increase current through power switch. Moreover they have to account for folks that are gonna be doing dumb things to it, like running from Vin(max) while overclocking to the limits.
Really minor thing: The chip most likely has no gold bonding wires anywhere in it. It's likely a flip-chip package, where there's a grid of teeny tiny BGA pads on the die itself, which get soldered to the substrate. After that, they usually get some sort of epoxy or other strain relief flowed between the die and the substrate to act as a strain relief. Finally, the chip gets the heat spreader put on, the substrate is balled, and then it's (eventually) soldered to the PCB. Fascinating stuff!
I worked as Service Engineer for Nikon Metrology for 2 years. It reminds me of the old time scanning my iPhone and using the picture as background or looking on the PCB of NeoGeo Pocket Color cartridges. It's nice to see this kind of technology explained and detailed for everyone.
My monitor sent me electromagnetic radiation to transmit information about Jeff's new video to my eyes. I call these frequencies of electromagnetic radition, JG rays.
An important distinction! Now that makes me wonder, what if you could use different materials instead of all copper with the routing complexities, to time-delay the signal to some amount of precision... or put a little water-based IC to slow down an optical signal or something like that :D
@@JeffGeerling It is difficult to use two different materials on the same layer of a PCB. PCBs are made by removing unwanted material, unlike 3D printing where you add material. Therefore I don't see any easy way to use two different materials. Even if there exists some alien technology that I'm not aware of, it won't be cheap for sure. It is much easier to time match PCB tracks.
You can use different materials outside the PCB. The other problems that you run into with traces being long and straight is that they become antennas however any length of wire will also become an antenna. So there's a whole additional layer of stuff you need to worry about which is why they sometimes run traces between ground planes in a PCB because it's the other commenter mentioned that Shields them somewhat from RF. Amateur radio deals a lot with velocity Factor of electrical propagation within different conductor types when you are building antennas. You start out building antennas in the HF and VHF bands where it's still a factor but not as critical a one. When you start looking at multiple gigahertz waveguides like the one built into the PCB work. The main reason for not including the antenna connector is that most people wouldn't use it and it reduces cost. The pi likely does not have a powerful enough transmitter to require recertification. It could have been certified with or without an external connector without difficulty. Lack of the connector was just cost and not having to make official support. You can transmit using a GPIO pin and violate FCC rules without an wifi antenna connection.
Umm, matching length guarantees matched timing. It depends on if it’s a bus or a group of multiple high speed series diff pairs in the same direction for TX or RX. Not sure what school you went to, but I wouldn’t use a board you designed if that’s your understanding of matched lengths on a pwb.
@@productivemonk5261 that's a mean and abusive comment. Length matching doesn't guarantee a time matching, because of something called electrodynamics. Go study that before questioning my qualifications. I don't design commercial products to sell, and I won't be selling anything to such a customer like you anyway. I'm a scientist working in the field of high energy physics at a top class research institute, I do design FPGA based high speed data acquisition systems, and we timing match the signal lines in picoseconds accuracy.
Mighty mite that RPi5. I seldom stop to look at its innards but it's worthy of admiration for the resourcefulness of its designers. Very informative video as usual.
The basic idea of a buck converter is pretty simple. It switches between two states, in one state the inductor charges in series with the load, in the other state the inductor discharges into the load. The capacitors act to smooth out the current drawn from the supply and the voltage delivered to the load. This allows the voltage to be reduced while keeping wasted power to a minimum. The output voltage is regulated by varying the duty cycle of the switching. A multi phase buck converter just has more than one inductor which switch at different times which gives a smoother and more stable result. You can't put big inductors or capacitors on an IC, hence why you see the pattern with the PMIC chip in the middle with the control logic and switching elements for a bunch of buck converters and then a bunch of Inductors and Capacitors surrounding it.
3:36 - the lattice pattern is a PCB layout feature (here the PCB being the chip package substrate). This "in-fill" is made that way for multiple purposes - too little copper would mean that the compression of the substrate during lamination would not be even, too much copper would make an asymmetric weight while electroplating the vias, and also large empty or full areas are making issues during etching. So designers choose some sort of infill.. you can see either a diamond shape mesh, or little rectangles placed at otherwise empty areas, even on outside of the PCBs.
The style of in-fill (lattice element size, proportion of filled / bare area) can also be used to fine-tune impedance of traces using it as a reference plain. Zach Peterson has some cool videos on this topic within the context of using Altium to design such features. Entirely likely traces within the memory IC are a different characteristic impedance than the I/O Bus lanes exposed at the pads - they’re running several instructions per input clock to generate the outputs requested at the bus.
Jeff is quoted as saying "... but I'm no engineer." Even though that may be true from a profession standpoint, I think your breadth of knowledge more than qualifies you as an intellectual equivalent. I call 'em as I see 'em.
Thanks for the boost; though I am definitely at the stage where I know how much I *don't* know, which is just about everything :D It's a dangerous stage to be at though-I know enough to break things a lot, but not quite enough to get them back working again every time haha
@@JeffGeerling , I totally get it and I empathize with you. But I think you are far humbler than you have to be. This is yet another reason why you are easy to subscribe and like.
As is often the case, thanks Jeff for doing these things so the rest of us don’t have to. This certainly helps to emphasise what impressive pieces of engineering these little SBCs are.
I LOVE IT JEFF, I was like, Whats on my screen, Wait...Jeff is watermarking so they don't "right click" or "screenshot" his x-ray, LOVE IT! Good move sir!
Not sure if the components on the differential data lines to the memory are capacitors. Quite often you see resistors in series with communication lines to reduce 'ringing'. Right now AlphaPhoenix has on both his channels some very (!!) good videos about impedance and he also briefly mentions this aspect in his (really) excellent talk. I highly suggest you'll look at those and also the first few comments as those are also a great addition to this. Anyway it is really great to see these boards X-rayed, so keep up the good work, Jeff.
AlphaPhoenix's videos are incredible. Great explanations and very visual ways to teach concepts that are practically impossible for my brain to grasp out of a book.
@@brewman467 Hmm I only know ferrite beads to be used to dampen HF noise. Like used in bridging power nets to components which have quite high frequency current spikes. For example a network chip. So it sounds a bit odd to me when you would use something to dampen high frequency signals. When used as resistor in series with the transmission line, you prevent 'rining' or reflections occuring multiple times.
The lattice structure is traces on different layers going from the memory to the SOC. It is common practice to not run traces parallel on different layers to minimize their capacitive coupling. The serpentine wires are also not just for differential pairs. Any time you have high speed data the length matching can ensure that multiple data paths will reach the chip at the same time, so it is easier to sync data transitions with the chip clock.
I design ICs for DC-DC converters for a living (major semiconductor manufacturer). That power delivery isn't mainly so different parts can quickly turn on and off. It's because these big SOCs have a bunch of rails (power supply nets) and need a fairly complicated PMIC (power management IC) to deliver power to all those rails and properly sequence all those rails at power up. Most of those inductors are for different channels of a bunch of buck converters (take higher voltage and step it down). See, you power a Raspberry PI with 5V. But no even remotely modern logic chips run on 5V. So, you gotta step the voltage down. And different parts of the chip want different rails. For example, the core logic probably want it's own rail, the DDR interface wants another, the IO another, etc. DC-DC converters and inductors seem complicated, but they're actually pretty simple. The way to think about inductors is they are the opposite of a capacitor. If you have an ideal capacitor and you try to change it's voltage, you need a certain amount of current for a certain amount of time. Inductors are like that, except for current. So, if you have an inductor doing a certain amount of current, it takes a certain difference in voltage across that inductor for a certain amount of time to change it's current. So, what you can do is charge an inductor up, then, since you're "storing current" you can discharge that current into a load in some controlled way to make an output at a different voltage than the input. You may have heard how you need suppression diodes for relays. That's because the coil of a relay is very inductive. When the relay is on, you're doing current through that inductor. When you turn it off, all that current needs to go somewhere. If you don't give it a controlled place to go, it will spike the voltage to something potentially dangerous for the electronics. So, the suppression diodes give it somewhere to go. We use inductors in similar ways to make all sorts of output voltages from input voltages. The output can be higher, lower, or inverted (and of magnitude greater than or less than) the input, depending on how we arrange things. Another way to think about a buck converter is imagine you have a series of pulses. If the pulses were high 100% of the time, the average would be just whatever the high voltage is. If it were low 100% of the time, the average would be whatever the low voltage is. So, if you make the high time some other fraction, you can make an average somewhere in between. Then, all you need is a lowpass filter to make DC rather than pulse train. Since it would be very inefficient to do that with an RC filter, you can use an LC filter to do it with much less loss.
I have been doing hobby PCB design for years, even dabbling into PCIe and other high speed protocols. Length matching is important in very high frequency applications, because if not length matched, some signals can literally arrive faster than the others, and then the data won't make any sense. Length matching by curling, as you've said, has it's own caviats, because they essentially act like antennae, so you need to be very careful where you route them (away from any analog signals, or other high speed traces, due to crosstalk), and ensure proper EMI insulation. Decoupling caps for power rails are there to smooth out any voltage spikes or dips, that can occur for example due to external EMI, non-ideal power supply or a billion other things. The coupling caps on the high speed rails on the other hand are to remove DC offset, that is unduced while measuring the voltage difference between those pairs (amongst other things). Regarding the size of IC dies and their packages - I'm sure you at some point have encountered a weird black blob on a PCB with traces leading to it. Those blobs are basically IC dies soldered directly to the PCB, without package. Their advantage is that they are super super small compared to packaged ones, their biggest downside is, that they are extremely fragile in that state (that's why they put that black goo over them, which is kind of the same plastic as the plastic IC package material). They are also much harder to route (and manufacture the PCB) since the "pins" are much, much smaller and closer together. On the power deliery, they use both inductors (L) and capacitors (C) (with other components) to form a charge pump, which is used to convert voltage (from higher to lower and vice versa), as well as LC filters to filter out any noise from switching power supplies (that most often operates at 125kHz, and some components, especially those that deal with high speeds or analog signals, doesn't like that).
One of the greatest features of DICOM I personally like - is an ability to precisely measure distances. In this case, you can measure all components and distances between its pins without disassembly or desoldering. What a great way for reverse-engineering! For some reason, not many doctors in my area are happy with this idea😅
Dr Jeff do you warm up your stethoscope before you place it on the Pi? 😂! Thanks for video and showing all the secrets of the Pi, even Redshirt Jeff is Green with envy. Have a great day!
I don’t know how possible it would be, but if you could get some of your tshirt designs on some LTT shirts, they are super comfy and I definitely would be purchasing one!
I wish you had used a BIG cursor in contrasting color to highlight everything you discussed. The tiny white dot was mostly invisible and impossible to follow on screen.
Sorry about that! I was trying to get in a re-take on that portion, but I've been in the middle of a move, so my main computer and all my monitors were not connected, and I had trouble getting the normal screen capture set up on my other Mac :(
Quite true! And I didn't even get to _why_ people do X-ray their electronics... I'm sure Raspberry Pi is sitting on a treasure trove of X-ray images of all their boards :)
The fact that the Pi is only 6 layers is pretty impressive especially given how complex that SoC is. My own hobbyist PCB designs are sometimes 8 layers! Then again, they do seem to use blind/buried vias, that definitely makes it easier
The caps beneath the SoC are most likely not some sort of filter caps, to filter out noise, which is spread to other components. Instead, they store power that is needed by the SoC during dynamic processes and deliver it via the shorted path possible. You are not mainly wrong, because this also results in better EMI performances, but the main reason they are placed there is to provide a bypass path for transient currents ...
This statement is not entirely correct. Decoupling and filtering are in essence the same thing. A decoupling circuit is a filter with a high input impedance and low output impedance.
@@foobarables You are correct. And I mentioned that as well by writing that his explanation is not wrong. But as an electronic design engineer I would not call this caps filter caps, although they act also as a filter in some sense.
Capacitors block DC because once they fully charge, they stop charging and both sides stop moving current if the voltage doesn't change. Inductors are the opposite, they are DC shorts but block AC (once frequencies go high enough for the particular inductor).
Ooh... I haven't thought about that, but it could be a nice thing to offer on redshirtjeff.com - I think in 2024 I'm going to revamp things on that end and offer more interesting stuff. (Also Teespring's service has not been great).
@@codyjlee Here's all I can get up in a short timeframe-this is 300 dpi, but it only goes up to 16x20 for now. I'd love to work with someone to make available larger prints next year. Just want to make sure they're decent quality!
If I can cobble together enough funding... I could do a 3D CT of the Pi too, then the sky's really the limit-it's fascinating what modern metrology labs can do.
@@JeffGeerlingthat would be awesome! :D Maybe you could find a sponsor who has a 3D CT scanner you can use, in exchange for showing off tech at their facility? Thank you again for all the interesting content you produce! 😊
Jeff, much respect to you. I am a EE flunkie (finished Comp Sci) so I had quite a bit of the EE curriculum (sadly I just didn't get the "official credentials" like those that hold the EE piece of paper). Your grasp of circuits and electronics amazes me! My understanding is you started in tech as a web developer (like front ends and UX web developer). I'm respectfully jealous of how much knowledge you have amassed on your own! Custom compiling linux kernels, studying circuit board layouts, etc... What's your secret? (I'm guessing probably just a 200 IQ). Always a fan and hats off to you man!
Haha no clue on IQ but mostly insatiable curiosity. My Dad always handed me broken stuff and parts, and it was up to me to figure out how they worked or how to fix them, so I got a leg up on that even before I got into software! I remember the first burn I got with a soldering iron was when I was about 8 working on a tiny FM transmitter kit I bought from Radio Shack! I do lack a lot of the book knowledge, which I think is important to be actually good at a skill and not just "can often make it work" level. I like to understand the whys too.
@@JeffGeerling Do you know the difference between a professional and an amateur? Answer - One gets paid for it and the other just knows it, sometimes probably better then the paid one. My motto is never stop learning.
Hi Jeff, awesome video! 👍👍 The RAM lines being a mixture of bent/squiggly/straight is to get their electrical length, for signal timing, to within the required tolerances for maximum transfer speeds.
Yes this. It's crazy that the speeds are so high that adding a few mm to the length of a trace can be critical to make sure all the related bits get to their destination at the same time.
How many layers is the PCB? Edit: and you said it a bit more in the vid lol. Awesome job!! Your channel has fast become my fav. Love the engineering channel too! Your dad is awesome and love the stories.
Hey Jeff, great video! The Xray and wonderful explanation made for a fantastic experience. You have a skill for explanation in a clean and concise way and you keep it light and entertaining! I’m not an rf engineer but I *think* the PCB based antenna, triangular ground plane cutout is a form of a waveguide. I could be totally wrong. 😂 Definitely interested in antenna design and it sounds like I need to read some more on it.
And that's just a theo-, JeffPat? Do I see cans of diet coke and notebooks of restaurant history details? In all seriousness, I really enjoyed this video. The more we understand how these things interconnect and work, the more we can pull crazy ideas through them.
Nice! I spent my PhD working on ways to improve the contrast resolution of micro-CT scans using research machines based on Nikon Metrology's scanners (looking for extremely small changes in mineral density in anything from extracted teeth to rolled-up parchment scrolls.) My postdoc friend started X-raying his food after finding a worm in his lunchtime apple one day.
@@boneappletee6416 once bitten (or faced with a recently-deceased half a worm in your apple), twice shy. Similarly, we used to get slugs coming into the kitchen at night through the pet flap, and now I don't walk barefoot when the lights are off.
A fun screenshot I saw on Reddit today mentioned that their high performance research computer running AI kept creating trains to solve traffic - reminded me of cargo belts and trains from Factorio 😂
Capacitor are use to remove DC offset because their output voltage depend of the change in voltage input (and the frequencies of the change to choose the capacitor value), not the absolute value of the input. Same principal is used in audio amplifier output, specially class A where you have only one transistor working only on a positive rail. With no signal, you output a DC signal around half the voltage (the offset), capacitor block DC ( and continuous signal will blow your amp). When the output go over or under the offset voltage, the capacitor will reproduce the same variation around the ground. In digital, the capacitor is used for decoupling the signal from any offset present in the signal ( aka ground noise ) on a high frequency low voltage binary signal.
That is only when used as a coupling capacitor. In Bypass applications they use stored energy to supply extra current when the IC outputs change state. A third use is in resonant (L/C, R/C or R/L/C) circuits to tune a circuit to a desired frequency.
@@JeffGeerling Experience is definitely the greatest teacher! :) I don't have any networking qualifications, but it's been a large part of my work for the past ~2 years.
inductors are there to resist the buildup of current, the mechanical analog of electric circuits known as "spintronics" uses some weights on arms instead, using momentum. they essentially are surge-protectors, so that something doesn't go from 0 to 100 amps [exaggeration] in an instant, and instead winds up from 0 to 100 in a bit less of an instant.
The reason for ethenet being transformer-coupled, is primarily because long runs between places can have quite different ideas what 'ground' is. And the differential inputs for differential logic signals only works properly if the 'common mode' voltage the two signals are floating on, is small enough to still allow the differencing amplfier to still 'take the difference'. Practical differencing amplifiers like this have a limited range over which they can accept signals whilst still working right, so a big enough common-mode on both wires can cause it to no longer be able to function. So, you break all the ground loops by just transformer-coupling your digital signals. And later, some bright spark realises that, if you're going to do that anyway, why not deliver DC power as common-mode DC? And PoE is born. Which works basically by avoiding a ground connection for the thing hanging out on the end of the run, powered by PoE. It can work fine with a big DC offset there, and it's ok. But this does mean you need transformers to physically connect 1xBaseT ethernet. (it's what the 'T' is for, right?). Building them into the port itself has made a lot of sense for a long while. But to send/receive data, you need a chip designed to handle the bipolar (ie, both positive and negative voltage, and so both-possible direction current) pulses that go through the transformers. And this is mostly what the PHY (often built into the MAC) chip does.
Great video! I think you misuse the word 'bonding wire'. I don't think the SoC uses bonding wires but rather is a 'flip-chip' that has the C4 balls connect to the package, that uses larger solder balls to connect to the PCB. Bonding wires are used for chips that have only 10 .. 20 I/O's
The power Management Integrated Circuit "PMIC" is a highly efficient switch mode power supply with minimal losses to provide all the voltages needed by the Pi from a single voltage supply. The capacitors assembled on the main Pi's Chip known as System on Chip "SoC " are for decoupling.
Just don't use the image to design a "transparent" case only to have it ripped off by a competitor who you now have to sue for big bucks. Not that that would ever happen to a company who makes iPhone cases. 😂
Hey Jeff, I'd love to see what's inside the large BGA packages. You might wanna try lapping the layers off and a using a microscope for some lovely die shots! It would look awesome on a T shirt aas well.
Definitely! Right now I'm still getting my feet wet with that kind of thing-the chemicals you need to use to do that well are quite dangerous, so I have laid back from that. But I want to do it :)
I worked at a company that did this. The chemicals needed are pretty dangerous (eg, hydrofluoric acid) and it's quite tricky to do the etch so it removes a single layer evenly across the entire die. Back in the day when I worked there, feature sizes were on the order of 100nm or bigger, so you could see individual transistors with an optical microscope. Now, with sub-10nm features, that's impossible.
Ken Shirriff would be a good one to talk to about that. He's done lots of those sorts of teardowns. And, while he does have a UA-cam channel, he's much better known for his blog and his work with CuriousMarc (highly recommended channel).
that lattice in the memory chips is most likely a grounded shield. some people have sanded through potted usb drives and sd cards often to recover data. and they grind through a top copper layer first. the lattice is used to use less copper than a full copper shield. in theory you can even measure the size of the holes to calculate the smallest wavelength it can protect against.
what is truely amazing, is that it *only* uses 6 layers. The last board my team built for a microserver used 12 layers.... my favorite quote: _it is simple to build something complex, yet is is complex to build something simple_
@@productivemonk5261Excellent! - did a communication backplane once with 32 layers. That almost bankrupted the manufacturer (100mil + 100mil, wall to wall high speed differential traces)
The squiggly lines you're talking about are traces, it depends on what the engineer intends, some are set that way as delay lines and some are uses as antenna array or in some cases used as a RF balancing circuit (this one is pretty rare and hard to accomplish). Sometimes the line delays are a way to avoid crosstalk from other layers but there are better ways to do that, too.
9:07 The key use of inductors is to efficiently convert between voltage and current. Without them you're left with dissipating excess voltage as heat (linear regulator), or using a much larger traditional transformer.
The Pi with a modified external (passive) antena may produce too powerful signals in range of like 20m or less. But not legal. But they *probably* won't know.
Did someone get that Jeff isn't an electronic engineer? 😅 still, he shows us these very cool x-ray pictures with decent explanations also for none engineers like me 👍
The one thing I was hoping for was built-in POE on the board without a hat, but i guess board space constraints made it a no go. Making a Pi board a little longer to add it on would be great say a RPI-5Poe version keep mounting holes in same location for hat bolt down compatibility and an exta set on the new longer end, all you need is a longer case. Sure I could buy a POE breakout brick or hat but that just makes it a pain in the A$$
Very few people use POE so it would make no sense to add it as standard. As very few people need It it would not be economic to make a separate special version either, it would be best to have that as a add on hat!
Those little 'pairs of capacitors' are not: They're pairs of resistors, implementing source impedance matching. These act to prevent the signals from 'ringing' on the wires - basically, same function as the dampers in your car's suspension. In this case, the signal is usually allowed to bounce off of the far end - and then ends up landing on these. It's part of impedance matching. Differential signals for logic are not AC coupled: to do that, you have something like Ethnernet, with transformers and a MAC which translates postive/negative pulses back to DC logic. For PCIe and friends (eg, USB3, TB, and some of the signals in a DDR bus: usually just the clock and or strobe) it's not really a 'differential signal' like the way that analogue differential signals work (where you have a 'hot' and a 'cold' wire), but rather it's properly called a 'complementory digital signal'. What this means, is that each of the pair are actually independent 'single-ended' DC logic signals (although often 'reduced swing' - lower voltage levels), and the property that makes them useful as a 'pair', is that one is high when the other is low (thus, 'complement' ) AND that transitions of both happens at basically as close to *exactly* the same time as can be arranged. Then, the point of routing them with wiggles, is that the two signals need to be recieved having exactly the same transmission delay along whatever path they individually take (in addition to that path being 'impedance matched!') so that the transitions arrive at the same time too. They are received as a differential signal, but they're usually sent as two normal digital output signals (maybe with differnent voltage levels) that just happen to be synchronously clocked at the same time. Doing this gives two major benefits, and was sort of a quantum leap in digital technology, as well. The first benefit is that the reception is quite good at rejecting a common-mode (same disruption to both sides of the pair) interference signal, whether it's electrostatic or electromagnetic. But the second, lesser-known benefit, is that by passing both wires more-or-less through the same region of space (ie, keeping them fairly close to each other) when the logic state switches, it doesn't cause a disruption to the total current down the pair. This is because, each of the two signals being a 'normal, single ended logic' (aka, DC between two levels, current changes with levels but is always flows in the same direction) signal, the total current down the pair becomes a constant so long as they always swap states (low voltage and current, high voltage and current) at the same time. This means the total current down the physical space the pair follows is mostly just constant DC, regardless of the logic activity. And THIS property, means that the pair does NOT emit it's own electro-magnetic radiation. If you like, the change in current on one wire, is cancelled out by the change of current next to it in the other wire, both changes move down the pair at the group velocity, and all wires that arn't between the two (which is all of them, notice!) therefore don't 'see' any net change in current. Therefore, no interference is emitted, **even when the changes are happening so fast that the pair length would otherwise be long enough to act as an antenna**. So, there you go - by making a pair of signals always switch at the same time, and also making each be 'impedance matched' (just stops resonance from the pulses bouncing back and forth and building up a standing wave), we can send data very fast beween two points, without the pair acting as an antenna and emitting a radio signal which would interfere with other circuits. This is usually used in conjunction with differential reception (better immunity to ALL other possible interference), but you can still use it even if the receiver is 'single ended'. What you do is put a 'load matching' resistance at the end of the complement signal that you're 'not using', and place that right nearby the pin that is receiving the signal that you are using (that 'dummy' load should be tuned to 'look' just like the equivalent resistance the single-ended chip receving the digital signal has, so the currents remain balanced at all times). Had people known about this back in the 80's, we'd have had much faster PC's originally. Many of the old-school 'high speed' MSI logic chips were limited by interference between parallel wires that they didn't, at the time, have a solution for, and this is that solution. They tended to be limited to low MHz, when their chips were already theoretically capable of 100's MHz, they just couldn't get them to run without immediately crashing due to the interference of non-impedance-matched traces acting like little antennas, ringing with resonance, and inducing interference in all nearby other traces. What a mess that was! And on top of that, they had 'ground bounce' which was causing the receiving chips to compare the incoming signal to a bad 'zero' reference which was anything but. On top of *all that*, complementory logic means the IO current for a chip using only it, has a constant current draw from the power supply, as the use of current is constant regardless of the logic states of the outputs. Guess what *wasn't* true back in those days? You guessed it - the power supply draw depended on the logic state of the output pins of the chip, so the logic activity modulated the power supply draw, causing the power supply to have noise on it too. So, once it was realized that complementory logic gets rid of all of these problems. It was 'discovered' that we could then use a much smaller voltage swing too - and further reduce noise, without losing reliabilty, and gain more energy efficiency at the same time. So that's why LVDS is the way it is. The final 'nail on the coffin' that lead to the amazing utility of PCIe, was the 8b/10b encoding scheme to insert the clock into the same pair as the data, so the receiver need only have the one logic signal to accurately and reliably figure out when to sample it. This is why both sides of the PCIe lane are totally independant - because there's no use clocking your reception of the RX signal at the same time you do the TX signal, especially if you don't actually know how long a delay it is to the other end of the link. And trying to fix the 'delay' by just sending the clock independantly - well, that's how SDRAM (including DDRx and LPDDRx) all still works: you have to send a copy of the clock along with the signals in each direction, so that the receiver can use *that* clock to properly receive the data. 8b/10b encoding does away with all of that. And so yeah, throw in a little housekeeping around auto-tuning the link (and auto-inverting the signal too!), and allowing transparent link-agglomeration (which is good for fault-tolerance also more bandwidth, and why a X16 card still works over X1) all automatically at the digital hardware level, and you have PCIe the way we know it. Sprinkle just a little protocol on top, for arranging DMA transfers directly to/from the memory controller, so as not to thrash the CPU with interrupts, (and while you're at it, add a way to do interrupts, too, for legacy PCI support) and you're basically there. But those little pairs of inline SMD parts are definitely resistors - probably in the range 20 to 90. Because PCIe *isn't* AC, and if you 'use' the source resistance of the chip, you can just supplement it with a little extra series resistance to make an impedance match which just causes the reflected-back signals to get absorbed, without having to have an L-pad, resistive divider, or transformer that you'd need to make the impedance match work in both directions. This usually means the receiver doesn't bother with an impedance match, because those resistors will do a good-enough job of catching the reflection and preventing them from re-reflecting back in the same direction as the data is flowing. This is 'good enough', to an engineer, often the very best kind of 'good'.
MIND-BENDINGLY EYE-OPENING!!!!! lol I was having a REALLY hard time seeing the things you were pointing out... I had to either increase or decrease my video cards video brightness (it only adjust the brightness of video playback, and not the rest of the screen or 3d rendered stuff like games!! I just discovered it on my AMD 6650XT in the AMD Adrenaline app under Audio & Video... it's been useful and I'm telling everyone about it lol) I was able to adjust it and see everything really well, but it would have been impossible to watch this without making any adjustments..... I wonder if this has to do with the YT stream, or my TV's settings (yes I'm using a 50" 4K TV as my computer screen.... but I sit about 7 feet away lol) .. I think it's the stream because everything else looks great, but I am CONSTANTLY having to adjust it when I watch UA-cam... which I do pretty much 24/7 lol ..... - I wonder if everyone else was able to see the different parts you pointed out just fine.... hrmmm I think HDR also has to do with this too.... which I have turned on in Windows - Maybe I should watch it again on my actual computer monitor... it's only 34" 1440p but it's got a 165hz refresh rate.. but I never use it really.... - - -Why am I tell you all this?? i have no idea!! LOL That was a really cool video tho Jeff!!! THANK YOU!!! :D
Good suggestions-honestly, I probably over-exposed the images a little bit (but I tried to bring out some of the darker details while preserving some highlights too, since many traces are so faint). But it's a tradeoff-since most of our displays are okay-ish at HDR, and I target all screens, I try to cram as much of the image data in there as possible. The raw TIFF files I got from the scanner contain a bit more detail.
You sure you haven't got a silly setting turned on? My samsung 4k monitor has a "eye saver" mode and screws all the colours up. Screws me around every time.
No, I am not a doctor, but I do prescribe a shirt or the new metallic print of the X-ray Pi 5: redshirtjeff.com/listing/x-ray-pi-5-metallic-print
It'd be nice if the shirts had a version with a larger "Portrait" view of the Pi, and perhaps a "negative" white print on a black shirt
It's a nice shirt, but I'll wait for the Casetify version...
Using Xray is a real cheat code. I used to maintain equipment in a machine shop/foundry and they had an Xray machine that would go through 3 inches of steel. I would occasionally Xray mechanical components that I had problems disassembling to find out what was inside.
FCC part 14 rules governing frequencies like 2.4ghz and 5.7 ghz are legal for enthusiast tinkering in the USA. You are simply not allowed to sell it as product without re-certifying. I get annoyed when people say things like this are 'illegal'. I thought you were a ham op or at least came from an RF background, you should know better.
Jeff, I just wanted to say I absolutely love the picture you chose for your redshirtjeff merch store banner 😂❤
4:16 Electrical engineer here. One small correction - those wiggles are for something called length matching. When you have a high speed group of signals that all need to get from point A to point B, they all need to be about the same length , so they get there at the same time. In this PCI-e example, they happen to be differential pairs as well, but that's not the reason why they are length matched. If you look closely at the RAM tracings you can see similar matchings there.
PS: You did mention its for length matching later in the video. Sorry. i wrote the comment before i got to that point.
Thank you for the comment either way! Differential signaling / timing can be a bit confusing, especially when the majority of my work on any kind of PCBs/breadboarding is in decidedly low-speed communication :)
@@JeffGeerling 1970's PCBs with speeds in the low megahertz range are much easier to understand. I think they tag those coupled differential pairs as a "network" in the design software, keeping them uniform, straight as possible, and on the same layer.
Have seen the term "MagJack" used for the integrated magnetic couplers in the RJ-45 interface housing.
Differential pairs do need to be length-matched, so it's not _wrong_ to say the squiggles are there because they're differential signals, just not the whole story.
@@hellterminator Should be length matched. When you're talking low speed you can get away with a bit of slop. Sometimes we're hand making cables, and RS-485 is very tolerant.
@@JeffGeerlingAlso regarding PCIe 3.0 being out of spec, I read in Raspberry Pi Forum a post by rpi engineer saying that clock jitter due to PLL used in the soc is the culprit
I run two Zeiss CT scanners, one can scan at sub-micron resolutions (Xradia)! Thanks for showing off this technology and the Metrology field as a whole!
Metrology is fascinating!
I thought metrology was the weather.
@@RowanHawkins Well it's a good thing they're close, because I also love meteorology! (which... I guess what's the study of meteors then???)
@@JeffGeerlingmeteoritics? 😂
@@JeffGeerlingastrophysics
I need to seriously stop just glancing at titles! I thought this said "I X-Rated My Computer" which I was like, I can respect that... Don't know that I'd make a video about it, but you know that's just me...
Wait, you didn’t know “Raspberry Pie” was going to be the next in the “American Pie” series?
Because Jeff was just looking to add some Bow-chicks-wow-wow to his page…. LMAO
A lot of small VIA's in a line are often a "fence" against unwanted signals propagating through the board between layers. A sort of faraday cage. The distance between the VIA's will be slightly less than ½ wavelength of what they want to block. This requires 2 (or more) ground planes which is not uncommon.
Very cool view of our electronics.. Thanks Jeff!
Been doing electronics design for years now, and it's kinda crazy all the steps you gotta take to get those pci-e lanes to behave under the worst conditions, but it's also crazy just how much wiggle room you get too. I know people were using just plain bodge wire on the pi4 back when it was first discovered to have pci-e, and interestingly pci-e even has support for flipping the wires of a pair, despite them being polarized.
Also, Ethernet magnetics are fascinating. My understanding is that the original intent was to deal with ground differentials, where the ground potential of a circuit could be 1000's of volts above the ground of another circuit. The PoE is a clever hack that uses the fact that you're basically scrubbing the voltage potential from the lines with the magnetics, meaning you can put whatever voltage difference you want across those lines. I know most poe uses either 24v for passive or 48v for active, but those voltages were mostly selected due to restrictions on high voltage lines in buildings (or at least that's my current understanding of it. Only source I have is friend who has been designing network circuits a decade longer than I have.). by sticking with 48v, it counts as low voltage, and in the majority of states, means it can be self-installed.
There is a lot more to it than that. 48v DC is a long standing voltage in copper Telecom circuits. It is the resting voltage provided by the LEC or Local Exchange Carrier from their switching centers to power all of the analog POTS lines around which the LEC's have to maintain service for emergency situations. That is why Switch offices are built like tanks. They have battery and generators on site to maintain power to all the analog phones connected to them. To make a POTS phone ring its sent 90v AC by the Switch.
The National Electric Code or NEC that sets those standards. The National Fire Code is to prevent and reduce damage from fires. Your local building code combines those with local community needs to determine to what standards work needs to be completed to. Who can work on something is often determined by insurance but generally if you are the property owner you can do all of your own work. You should do it to standard of your local building code but it isn't required unless its commercial property. If you do it to less than the standard and its determined your work was at fault then insurance may not pay out or if its work done for someone else you may become liable for the loss.
Low Voltage also inclues 110v/120v/240v AC service. 208v 3-phase AC and over 100v DC I believe are Medium Voltage but it has been a while since I looked it up.
The voltages have nothing to do with running particular types of voltage in a building.
Note that the 1500V commonly quoted for Ethernet isolation is a test voltage, *NOT* a working voltage. It's the same as the 1500V test voltage specified in most IEC standards for "basic insulation" and half that normally specified for "reinforced insulation".
You can have passive 48V POE also. Though passive POE is sort of an gray area type of thing and doesn't actually have any hard and fast rules. I've even seen people do 12V passive POE. IEEE 802.3 always has POE as active. You're right that 48V is picked because it's low enough voltage it can be self installed because it's considered low voltage in most places. The other side of that is that the higher the voltage, the more power you can deliver. That's because P=VI. Voltage drop is caused by wire resistance. You could increase wire diameter to decrease resistance, but that's not really an option for ethernet wiring. So, you really want I to be as low as possible. So, you up V to as high as you reasonably can. In either case, you'll have a DC-DC converter at the load to efficiently step that down to whatever you need.
@@ccoder4953 Operating passive PoE at those higher voltages isn't a great idea though, as it will cause additional arcing when you plug in that will wear the contacts. Standards-compliant PoE uses a lower probe voltage, and only switches up to 48V after negotiation.
It's very annoying to me that the Pi Foundation apparently went to the trouble to design a custom power management IC with Renesas but couldn't be arsed to include support for a step-down converter in it so that you could use any totally standard 27W or greater PD supply (9V3A) instead of needing the wonky custom 5V5A profile their own adapter uses, just to save a few cents.
Great video, though! As an electrical engineer, no major glaring issues that I noticed. Accurate enough for a youtube video! At least one or two of the chips you mentioned as having bond wires are actually probably flip-chip and what you're seeing are the breakout traces in the package (with no flying bond wires) but it's a minor detail and I'd either need to know more about the chips in question or take a closer look at cleaner x-rays of just the bare chips to be sure.
THIS!!! Cannot agree more, apparently they don't care for e-waste, but only profit. Cannot imagine one logical reason for this wonky setup. Getting cost down my ass.
Just a little correction: Raspberry Pi Foundation are the nonprofit good guys behind all the OSS goodness and education support. The assholes who make proprietary solutions (like the aforementioned power profile or the FPC PCI-e connector) and shitty products (Pi4 official case that overheats the Pi even at idle, Pi 4 official case fan that barely helps but is very noisy, official display with terrible viewing angles and non-square pixels,...), who ditched their community for industry customers during the chip shortage, and who lie and play games, are the for profit company Raspberry Pi *Trading.*
I bet USB PD IP cost is far from "cents"..
@@Mr.Leeroy That's the point; the Pi is _already_ a USB PD device and uses the protocol to negotiate its profiles, they have just chosen to make it report a non-standard profile that nobody else uses so they don't have to deal with voltage conversion. Supporting this would take an inductor, a few other small support passives, and a very slightly more capable power IC (cents, like I said). Every smartphone that supports more than 15W charging managed to fit this into their much tinier mainboards, the Pi foundation just didn't consider it a priority and likely assume they are large enough to strong-arm the rest of the industry into accommodating them.
The cynical take is they did it deliberately to sell more power supplies which likely have much higher margins than the Pi itself, but I don't know if I'd go quite that far myself.
@@siberx4 I was talking about proper IP block for their custom PMIC, that would be an investment in it self.
If their engineers say that there was no spare PCB real estate, I believe them.. Remember, that they already had to go with not 2, not even 4, but 6 layers to cram everything into spots where everyone expect every little thing. 6+ layers production is not a joke and definitely not cents more expensive.
Also their claim that wide voltage input rage would produce more heat is sound, as efficiency would drop almost certainly very dramatically with ratios Vin/Vout > 2, and buck costs are only rising at the same rate as we increase current through power switch. Moreover they have to account for folks that are gonna be doing dumb things to it, like running from Vin(max) while overclocking to the limits.
Really minor thing: The chip most likely has no gold bonding wires anywhere in it. It's likely a flip-chip package, where there's a grid of teeny tiny BGA pads on the die itself, which get soldered to the substrate. After that, they usually get some sort of epoxy or other strain relief flowed between the die and the substrate to act as a strain relief. Finally, the chip gets the heat spreader put on, the substrate is balled, and then it's (eventually) soldered to the PCB. Fascinating stuff!
I worked as Service Engineer for Nikon Metrology for 2 years. It reminds me of the old time scanning my iPhone and using the picture as background or looking on the PCB of NeoGeo Pocket Color cartridges. It's nice to see this kind of technology explained and detailed for everyone.
My monitor sent me electromagnetic radiation to transmit information about Jeff's new video to my eyes.
I call these frequencies of electromagnetic radition, JG rays.
WOW!!! Mine does the SAME THING!!!! Do you think other people's screen do this too??? lol
@@Nobe_Oddy I think we need to investigate this.
@@MarcoGPUtuber I reckon we can get 3 or 4 research papers on this!
Love it Jeff. We're featuring it on the Raspberry Pi blog tomorrow and we've got a reaction quote from the engineer who designed Pi 5!
Ooh nice! I just saw it! www.raspberrypi.com/news/what-does-a-raspberry-pi-5-x-ray-reveal/
You'll never catch me, Jeff. *furiously scratches away at hidden antenna traces*
You hacker!
@@JeffGeerling I love how that's a compliment in this community 😁
Actually differential pairs are not length matched, they're time matched. The time delay between the pair of lines should be as small as possible.
An important distinction! Now that makes me wonder, what if you could use different materials instead of all copper with the routing complexities, to time-delay the signal to some amount of precision... or put a little water-based IC to slow down an optical signal or something like that :D
@@JeffGeerling It is difficult to use two different materials on the same layer of a PCB. PCBs are made by removing unwanted material, unlike 3D printing where you add material. Therefore I don't see any easy way to use two different materials. Even if there exists some alien technology that I'm not aware of, it won't be cheap for sure. It is much easier to time match PCB tracks.
You can use different materials outside the PCB. The other problems that you run into with traces being long and straight is that they become antennas however any length of wire will also become an antenna. So there's a whole additional layer of stuff you need to worry about which is why they sometimes run traces between ground planes in a PCB because it's the other commenter mentioned that Shields them somewhat from RF. Amateur radio deals a lot with velocity Factor of electrical propagation within different conductor types when you are building antennas. You start out building antennas in the HF and VHF bands where it's still a factor but not as critical a one. When you start looking at multiple gigahertz waveguides like the one built into the PCB work. The main reason for not including the antenna connector is that most people wouldn't use it and it reduces cost. The pi likely does not have a powerful enough transmitter to require recertification. It could have been certified with or without an external connector without difficulty. Lack of the connector was just cost and not having to make official support. You can transmit using a GPIO pin and violate FCC rules without an wifi antenna connection.
Umm, matching length guarantees matched timing. It depends on if it’s a bus or a group of multiple high speed series diff pairs in the same direction for TX or RX. Not sure what school you went to, but I wouldn’t use a board you designed if that’s your understanding of matched lengths on a pwb.
@@productivemonk5261 that's a mean and abusive comment. Length matching doesn't guarantee a time matching, because of something called electrodynamics. Go study that before questioning my qualifications. I don't design commercial products to sell, and I won't be selling anything to such a customer like you anyway. I'm a scientist working in the field of high energy physics at a top class research institute, I do design FPGA based high speed data acquisition systems, and we timing match the signal lines in picoseconds accuracy.
Have you seen CuriousMarc's video on 3D x-raying some apollo gear? It's absolutely fascinating!
Mighty mite that RPi5. I seldom stop to look at its innards but it's worthy of admiration for the resourcefulness of its designers. Very informative video as usual.
The basic idea of a buck converter is pretty simple. It switches between two states, in one state the inductor charges in series with the load, in the other state the inductor discharges into the load. The capacitors act to smooth out the current drawn from the supply and the voltage delivered to the load. This allows the voltage to be reduced while keeping wasted power to a minimum. The output voltage is regulated by varying the duty cycle of the switching.
A multi phase buck converter just has more than one inductor which switch at different times which gives a smoother and more stable result.
You can't put big inductors or capacitors on an IC, hence why you see the pattern with the PMIC chip in the middle with the control logic and switching elements for a bunch of buck converters and then a bunch of Inductors and Capacitors surrounding it.
Game Theory pun made me chuckle. I was not aware that some ethernet jacks have the filtering built in. Very cool.
Dr. Geerling Pi D. is in the house!
3:36 - the lattice pattern is a PCB layout feature (here the PCB being the chip package substrate). This "in-fill" is made that way for multiple purposes - too little copper would mean that the compression of the substrate during lamination would not be even, too much copper would make an asymmetric weight while electroplating the vias, and also large empty or full areas are making issues during etching. So designers choose some sort of infill.. you can see either a diamond shape mesh, or little rectangles placed at otherwise empty areas, even on outside of the PCBs.
I also noticed on Twitter that someone had desoldered one of those chips, and that pattern is visible on the underside!
The style of in-fill (lattice element size, proportion of filled / bare area) can also be used to fine-tune impedance of traces using it as a reference plain. Zach Peterson has some cool videos on this topic within the context of using Altium to design such features.
Entirely likely traces within the memory IC are a different characteristic impedance than the I/O Bus lanes exposed at the pads - they’re running several instructions per input clock to generate the outputs requested at the bus.
Jeff is quoted as saying "... but I'm no engineer." Even though that may be true from a profession standpoint, I think your breadth of knowledge more than qualifies you as an intellectual equivalent. I call 'em as I see 'em.
Thanks for the boost; though I am definitely at the stage where I know how much I *don't* know, which is just about everything :D
It's a dangerous stage to be at though-I know enough to break things a lot, but not quite enough to get them back working again every time haha
@@JeffGeerling , I totally get it and I empathize with you. But I think you are far humbler than you have to be. This is yet another reason why you are easy to subscribe and like.
As is often the case, thanks Jeff for doing these things so the rest of us don’t have to. This certainly helps to emphasise what impressive pieces of engineering these little SBCs are.
I LOVE IT JEFF, I was like, Whats on my screen, Wait...Jeff is watermarking so they don't "right click" or "screenshot" his x-ray, LOVE IT! Good move sir!
13:01 it is true, you can learn so much just from changing perspective.
Not sure if the components on the differential data lines to the memory are capacitors.
Quite often you see resistors in series with communication lines to reduce 'ringing'.
Right now AlphaPhoenix has on both his channels some very (!!) good videos about impedance and he also briefly mentions this aspect in his (really) excellent talk.
I highly suggest you'll look at those and also the first few comments as those are also a great addition to this.
Anyway it is really great to see these boards X-rayed, so keep up the good work, Jeff.
AlphaPhoenix's videos are incredible. Great explanations and very visual ways to teach concepts that are practically impossible for my brain to grasp out of a book.
If the component is in series with the data line then most likely those components are ferrite beads.
@@brewman467 Hmm I only know ferrite beads to be used to dampen HF noise.
Like used in bridging power nets to components which have quite high frequency current spikes.
For example a network chip.
So it sounds a bit odd to me when you would use something to dampen high frequency signals.
When used as resistor in series with the transmission line, you prevent 'rining' or reflections occuring multiple times.
@@TD-er OK, I think that makes sense.
The lattice structure is traces on different layers going from the memory to the SOC. It is common practice to not run traces parallel on different layers to minimize their capacitive coupling. The serpentine wires are also not just for differential pairs. Any time you have high speed data the length matching can ensure that multiple data paths will reach the chip at the same time, so it is easier to sync data transitions with the chip clock.
I design ICs for DC-DC converters for a living (major semiconductor manufacturer). That power delivery isn't mainly so different parts can quickly turn on and off. It's because these big SOCs have a bunch of rails (power supply nets) and need a fairly complicated PMIC (power management IC) to deliver power to all those rails and properly sequence all those rails at power up. Most of those inductors are for different channels of a bunch of buck converters (take higher voltage and step it down). See, you power a Raspberry PI with 5V. But no even remotely modern logic chips run on 5V. So, you gotta step the voltage down. And different parts of the chip want different rails. For example, the core logic probably want it's own rail, the DDR interface wants another, the IO another, etc.
DC-DC converters and inductors seem complicated, but they're actually pretty simple. The way to think about inductors is they are the opposite of a capacitor. If you have an ideal capacitor and you try to change it's voltage, you need a certain amount of current for a certain amount of time. Inductors are like that, except for current. So, if you have an inductor doing a certain amount of current, it takes a certain difference in voltage across that inductor for a certain amount of time to change it's current. So, what you can do is charge an inductor up, then, since you're "storing current" you can discharge that current into a load in some controlled way to make an output at a different voltage than the input. You may have heard how you need suppression diodes for relays. That's because the coil of a relay is very inductive. When the relay is on, you're doing current through that inductor. When you turn it off, all that current needs to go somewhere. If you don't give it a controlled place to go, it will spike the voltage to something potentially dangerous for the electronics. So, the suppression diodes give it somewhere to go. We use inductors in similar ways to make all sorts of output voltages from input voltages. The output can be higher, lower, or inverted (and of magnitude greater than or less than) the input, depending on how we arrange things.
Another way to think about a buck converter is imagine you have a series of pulses. If the pulses were high 100% of the time, the average would be just whatever the high voltage is. If it were low 100% of the time, the average would be whatever the low voltage is. So, if you make the high time some other fraction, you can make an average somewhere in between. Then, all you need is a lowpass filter to make DC rather than pulse train. Since it would be very inefficient to do that with an RC filter, you can use an LC filter to do it with much less loss.
Those micro HDMI ports look so happy to be here.
this is really cool to see in such high detail!
I have been doing hobby PCB design for years, even dabbling into PCIe and other high speed protocols.
Length matching is important in very high frequency applications, because if not length matched, some signals can literally arrive faster than the others, and then the data won't make any sense. Length matching by curling, as you've said, has it's own caviats, because they essentially act like antennae, so you need to be very careful where you route them (away from any analog signals, or other high speed traces, due to crosstalk), and ensure proper EMI insulation.
Decoupling caps for power rails are there to smooth out any voltage spikes or dips, that can occur for example due to external EMI, non-ideal power supply or a billion other things. The coupling caps on the high speed rails on the other hand are to remove DC offset, that is unduced while measuring the voltage difference between those pairs (amongst other things).
Regarding the size of IC dies and their packages - I'm sure you at some point have encountered a weird black blob on a PCB with traces leading to it. Those blobs are basically IC dies soldered directly to the PCB, without package. Their advantage is that they are super super small compared to packaged ones, their biggest downside is, that they are extremely fragile in that state (that's why they put that black goo over them, which is kind of the same plastic as the plastic IC package material). They are also much harder to route (and manufacture the PCB) since the "pins" are much, much smaller and closer together.
On the power deliery, they use both inductors (L) and capacitors (C) (with other components) to form a charge pump, which is used to convert voltage (from higher to lower and vice versa), as well as LC filters to filter out any noise from switching power supplies (that most often operates at 125kHz, and some components, especially those that deal with high speeds or analog signals, doesn't like that).
You know what they say on EEVbog,
Don't turn it on !
X-ray it apart !
On serious note i wish Dave took a look at it on a video.
This is amazing! I want a phone case with the x-ray images of RPi 5
One of the greatest features of DICOM I personally like - is an ability to precisely measure distances. In this case, you can measure all components and distances between its pins without disassembly or desoldering. What a great way for reverse-engineering! For some reason, not many doctors in my area are happy with this idea😅
I can see how this tech can be used in advanced imaging and computer designs, Great Explanation.👍👍
Wait until some phone case company screenshots the thumbnail and crops it to use the X-Ray picture
Dr Jeff do you warm up your stethoscope before you place it on the Pi? 😂!
Thanks for video and showing all the secrets of the Pi, even Redshirt Jeff is Green with envy.
Have a great day!
4:58
insert *I understood that reference* meme
I don’t know how possible it would be, but if you could get some of your tshirt designs on some LTT shirts, they are super comfy and I definitely would be purchasing one!
9:35 the happiest micro hdmi connectors I've ever seen
If we see a Casetify Raspberry Pi 5 X-ray skin, we'll know where they -got- stole it xD
Differential data is sent as a pair of voltages, one normal, the other is inverted. This improves noise immunity.
this was awesome to watch while holding and comparing the xray to a pi 5 in person
I wish you had used a BIG cursor in contrasting color to highlight everything you discussed. The tiny white dot was mostly invisible and impossible to follow on screen.
Sorry about that! I was trying to get in a re-take on that portion, but I've been in the middle of a move, so my main computer and all my monitors were not connected, and I had trouble getting the normal screen capture set up on my other Mac :(
Great photo for the thumbnail
Important for safety critical & secure components!
Quite true! And I didn't even get to _why_ people do X-ray their electronics... I'm sure Raspberry Pi is sitting on a treasure trove of X-ray images of all their boards :)
@@JeffGeerling we have to petition them to release the images! 😁 For SCIENCE! (and a really cool desktop wallpaper for my RPi 👀)
What a cool look at the Pi, great work Jeff. And that's some awesome merch!
Cool! Really amazing! Lots of smart people. I'm always amazed at the complexity underneath what we regularly use and think of as normal.
The fact that the Pi is only 6 layers is pretty impressive especially given how complex that SoC is. My own hobbyist PCB designs are sometimes 8 layers! Then again, they do seem to use blind/buried vias, that definitely makes it easier
This was waaaay over the top of my head. But I can imagine this would be super interesting for all the people in the field that understand this!
I love that Game Theory reference :). Nice video. Maybe I will buy a Pi 5 if it is in stock localy.
The caps beneath the SoC are most likely not some sort of filter caps, to filter out noise, which is spread to other components. Instead, they store power that is needed by the SoC during dynamic processes and deliver it via the shorted path possible. You are not mainly wrong, because this also results in better EMI performances, but the main reason they are placed there is to provide a bypass path for transient currents ...
This statement is not entirely correct. Decoupling and filtering are in essence the same thing. A decoupling circuit is a filter with a high input impedance and low output impedance.
@@foobarables You are correct. And I mentioned that as well by writing that his explanation is not wrong. But as an electronic design engineer I would not call this caps filter caps, although they act also as a filter in some sense.
Capacitors block DC because once they fully charge, they stop charging and both sides stop moving current if the voltage doesn't change.
Inductors are the opposite, they are DC shorts but block AC (once frequencies go high enough for the particular inductor).
All this complexity.... In a computer that is sub $100 USD.... looking at this tiny stuff really makes you appreciate AMD's Threadripper...
I'd love to have one of those x-ray images on a metal print for my office wall!
Ooh... I haven't thought about that, but it could be a nice thing to offer on redshirtjeff.com - I think in 2024 I'm going to revamp things on that end and offer more interesting stuff. (Also Teespring's service has not been great).
@@JeffGeerling you can already count on an order if you do that!
It would be to covet.
@@JeffGeerling I would love to 3d print a lithophane using the image as well. Any way you could release the images? I'd be willing to pay.
@@codyjlee Here's all I can get up in a short timeframe-this is 300 dpi, but it only goes up to 16x20 for now. I'd love to work with someone to make available larger prints next year. Just want to make sure they're decent quality!
This brings up a good subject. It would be great to see SBC SoCs with memory on them. Would greatly simplify the boards.
dbrand x Geerling collab confirmed!!111
Thanks for adding actual captions for the Deaf.
I want to zoom through those edge-on views of the board like a sky taxi in The FifthElement! There’s an AI that can do that ...
If I can cobble together enough funding... I could do a 3D CT of the Pi too, then the sky's really the limit-it's fascinating what modern metrology labs can do.
@@JeffGeerlingthat would be awesome! :D Maybe you could find a sponsor who has a 3D CT scanner you can use, in exchange for showing off tech at their facility?
Thank you again for all the interesting content you produce! 😊
Jeff, much respect to you. I am a EE flunkie (finished Comp Sci) so I had quite a bit of the EE curriculum (sadly I just didn't get the "official credentials" like those that hold the EE piece of paper). Your grasp of circuits and electronics amazes me! My understanding is you started in tech as a web developer (like front ends and UX web developer). I'm respectfully jealous of how much knowledge you have amassed on your own! Custom compiling linux kernels, studying circuit board layouts, etc... What's your secret? (I'm guessing probably just a 200 IQ). Always a fan and hats off to you man!
Haha no clue on IQ but mostly insatiable curiosity. My Dad always handed me broken stuff and parts, and it was up to me to figure out how they worked or how to fix them, so I got a leg up on that even before I got into software!
I remember the first burn I got with a soldering iron was when I was about 8 working on a tiny FM transmitter kit I bought from Radio Shack!
I do lack a lot of the book knowledge, which I think is important to be actually good at a skill and not just "can often make it work" level. I like to understand the whys too.
@@JeffGeerling Do you know the difference between a professional and an amateur? Answer - One gets paid for it and the other just knows it, sometimes probably better then the paid one. My motto is never stop learning.
Hi Jeff, awesome video! 👍👍 The RAM lines being a mixture of bent/squiggly/straight is to get their electrical length, for signal timing, to within the required tolerances for maximum transfer speeds.
Yes this. It's crazy that the speeds are so high that adding a few mm to the length of a trace can be critical to make sure all the related bits get to their destination at the same time.
How many layers is the PCB?
Edit: and you said it a bit more in the vid lol. Awesome job!! Your channel has fast become my fav. Love the engineering channel too! Your dad is awesome and love the stories.
Really loved that Game Theory reference right there 😂
It's only a theory!
Hey Jeff, great video! The Xray and wonderful explanation made for a fantastic experience. You have a skill for explanation in a clean and concise way and you keep it light and entertaining!
I’m not an rf engineer but I *think* the PCB based antenna, triangular ground plane cutout is a form of a waveguide. I could be totally wrong. 😂 Definitely interested in antenna design and it sounds like I need to read some more on it.
Now this is what the deep dive of this Raspberry Pi…
And that's just a theo-, JeffPat? Do I see cans of diet coke and notebooks of restaurant history details?
In all seriousness, I really enjoyed this video. The more we understand how these things interconnect and work, the more we can pull crazy ideas through them.
Nice! I spent my PhD working on ways to improve the contrast resolution of micro-CT scans using research machines based on Nikon Metrology's scanners (looking for extremely small changes in mineral density in anything from extracted teeth to rolled-up parchment scrolls.) My postdoc friend started X-raying his food after finding a worm in his lunchtime apple one day.
I'm definitely on the same level of paranoid as your friend 😂
@@boneappletee6416 once bitten (or faced with a recently-deceased half a worm in your apple), twice shy.
Similarly, we used to get slugs coming into the kitchen at night through the pet flap, and now I don't walk barefoot when the lights are off.
The epic dialog in this video is at 08:03 "I wouldn't recommend it"
This makes me want to play Factorio.
It is like a production line, just for bits and bytes instead of hardware!
A fun screenshot I saw on Reddit today mentioned that their high performance research computer running AI kept creating trains to solve traffic - reminded me of cargo belts and trains from Factorio 😂
Capacitor are use to remove DC offset because their output voltage depend of the change in voltage input (and the frequencies of the change to choose the capacitor value), not the absolute value of the input.
Same principal is used in audio amplifier output, specially class A where you have only one transistor working only on a positive rail.
With no signal, you output a DC signal around half the voltage (the offset), capacitor block DC ( and continuous signal will blow your amp). When the output go over or under the offset voltage, the capacitor will reproduce the same variation around the ground.
In digital, the capacitor is used for decoupling the signal from any offset present in the signal ( aka ground noise ) on a high frequency low voltage binary signal.
That is only when used as a coupling capacitor. In Bypass applications they use stored energy to supply extra current when the IC outputs change state.
A third use is in resonant (L/C, R/C or R/L/C) circuits to tune a circuit to a desired frequency.
It's cute that you have access to a raspberry pi at all. you have more than my country has.
Fascinating! 🧑🔬
Amazing video Jeff. Love it!
"Thanks Crohn's"... I feel noticed! ❤ Hope things are going well for you Jeff!
I always thought you had to be an engineer as you are quite knowledgeable overall
Son of an engineer-but I'm a software developer by trade, didn't ever study for 'real' engineering, only learned through experience :)
@@JeffGeerling Experience is definitely the greatest teacher! :)
I don't have any networking qualifications, but it's been a large part of my work for the past ~2 years.
inductors are there to resist the buildup of current, the mechanical analog of electric circuits known as "spintronics" uses some weights on arms instead, using momentum. they essentially are surge-protectors, so that something doesn't go from 0 to 100 amps [exaggeration] in an instant, and instead winds up from 0 to 100 in a bit less of an instant.
The reason for ethenet being transformer-coupled, is primarily because long runs between places can have quite different ideas what 'ground' is. And the differential inputs for differential logic signals only works properly if the 'common mode' voltage the two signals are floating on, is small enough to still allow the differencing amplfier to still 'take the difference'. Practical differencing amplifiers like this have a limited range over which they can accept signals whilst still working right, so a big enough common-mode on both wires can cause it to no longer be able to function.
So, you break all the ground loops by just transformer-coupling your digital signals.
And later, some bright spark realises that, if you're going to do that anyway, why not deliver DC power as common-mode DC? And PoE is born. Which works basically by avoiding a ground connection for the thing hanging out on the end of the run, powered by PoE. It can work fine with a big DC offset there, and it's ok.
But this does mean you need transformers to physically connect 1xBaseT ethernet. (it's what the 'T' is for, right?). Building them into the port itself has made a lot of sense for a long while. But to send/receive data, you need a chip designed to handle the bipolar (ie, both positive and negative voltage, and so both-possible direction current) pulses that go through the transformers. And this is mostly what the PHY (often built into the MAC) chip does.
Great video!
I think you misuse the word 'bonding wire'. I don't think the SoC uses bonding wires but rather is a 'flip-chip' that has the C4 balls connect to the package, that uses larger solder balls to connect to the PCB. Bonding wires are used for chips that have only 10 .. 20 I/O's
Osteoporosis and crohns best friends forever. My hips are killing me. Thanks for the distraction
The power Management Integrated Circuit "PMIC" is a highly efficient switch mode power supply with minimal losses to provide all the voltages needed by the Pi from a single voltage supply.
The capacitors assembled on the main Pi's Chip known as System on Chip "SoC " are for decoupling.
i think you are safe from the fcc because as long as you stay within the frequency ranges of the wifi there should not be any problem.
Just don't use the image to design a "transparent" case only to have it ripped off by a competitor who you now have to sue for big bucks. Not that that would ever happen to a company who makes iPhone cases. 😂
Gee, now has that ever happened? I mean, what kind of jerks would ... oh yeah 😂
@@SchoolforHackers 😂
Hey Jeff,
I'd love to see what's inside the large BGA packages. You might wanna try lapping the layers off and a using a microscope for some lovely die shots!
It would look awesome on a T shirt aas well.
Definitely! Right now I'm still getting my feet wet with that kind of thing-the chemicals you need to use to do that well are quite dangerous, so I have laid back from that. But I want to do it :)
I worked at a company that did this. The chemicals needed are pretty dangerous (eg, hydrofluoric acid) and it's quite tricky to do the etch so it removes a single layer evenly across the entire die.
Back in the day when I worked there, feature sizes were on the order of 100nm or bigger, so you could see individual transistors with an optical microscope. Now, with sub-10nm features, that's impossible.
@@dfs-comedy Nice! And yeah, nowadays you just see different colors of light reflecting off everything :)
Ken Shirriff would be a good one to talk to about that. He's done lots of those sorts of teardowns. And, while he does have a UA-cam channel, he's much better known for his blog and his work with CuriousMarc (highly recommended channel).
Some people design a board, and some look what the incredible work they did.
that lattice in the memory chips is most likely a grounded shield. some people have sanded through potted usb drives and sd cards often to recover data. and they grind through a top copper layer first. the lattice is used to use less copper than a full copper shield. in theory you can even measure the size of the holes to calculate the smallest wavelength it can protect against.
6 layers?!? That's crazy. It's like looking at a microscopic version of the Dallas High Five Interchange.
what is truely amazing, is that it *only* uses 6 layers. The last board my team built for a microserver used 12 layers....
my favorite quote: _it is simple to build something complex, yet is is complex to build something simple_
Try working with 22 layers, large server backplanes have been doing this for 30 years.
@@productivemonk5261Excellent! - did a communication backplane once with 32 layers. That almost bankrupted the manufacturer (100mil + 100mil, wall to wall high speed differential traces)
Love the Jeff Geerling watermark. Afraid of being Castefied? ;-)
The squiggly lines you're talking about are traces, it depends on what the engineer intends, some are set that way as delay lines and some are uses as antenna array or in some cases used as a RF balancing circuit (this one is pretty rare and hard to accomplish). Sometimes the line delays are a way to avoid crosstalk from other layers but there are better ways to do that, too.
9:07 The key use of inductors is to efficiently convert between voltage and current. Without them you're left with dissipating excess voltage as heat (linear regulator), or using a much larger traditional transformer.
Really cool video, Jeff!
The Pi with a modified external (passive) antena may produce too powerful signals in range of like 20m or less.
But not legal. But they *probably* won't know.
I'm wanting to design my own PCB for a project, mostly just because I can. I can't even imagine the engineering that goes into designing an IC.
Did someone get that Jeff isn't an electronic engineer? 😅 still, he shows us these very cool x-ray pictures with decent explanations also for none engineers like me 👍
Pretty amazing for something that costs US$60 or so 🤯
I wonder if future castify cases will have a subtle, blurry 'Jeff Geerling' splayed across them....
Fascinating! Thank you!
If Jeff spoke with a southern Alabama accent then he would be Destin from Smarter Everyday. Good video Jeff
As a simplistic rule-of-thumb, capacitors stabilize the voltage while inductors stabilize the current.
The one thing I was hoping for was built-in POE on the board without a hat, but i guess board space constraints made it a no go. Making a Pi board a little longer to add it on would be great say a RPI-5Poe version keep mounting holes in same location for hat bolt down compatibility and an exta set on the new longer end, all you need is a longer case. Sure I could buy a POE breakout brick or hat but that just makes it a pain in the A$$
Very few people use POE so it would make no sense to add it as standard. As very few people need It it would not be economic to make a separate special version either, it would be best to have that as a add on hat!
Those little 'pairs of capacitors' are not: They're pairs of resistors, implementing source impedance matching. These act to prevent the signals from 'ringing' on the wires - basically, same function as the dampers in your car's suspension. In this case, the signal is usually allowed to bounce off of the far end - and then ends up landing on these.
It's part of impedance matching. Differential signals for logic are not AC coupled: to do that, you have something like Ethnernet, with transformers and a MAC which translates postive/negative pulses back to DC logic.
For PCIe and friends (eg, USB3, TB, and some of the signals in a DDR bus: usually just the clock and or strobe) it's not really a 'differential signal' like the way that analogue differential signals work (where you have a 'hot' and a 'cold' wire), but rather it's properly called a 'complementory digital signal'.
What this means, is that each of the pair are actually independent 'single-ended' DC logic signals (although often 'reduced swing' - lower voltage levels), and the property that makes them useful as a 'pair', is that one is high when the other is low (thus, 'complement' ) AND that transitions of both happens at basically as close to *exactly* the same time as can be arranged.
Then, the point of routing them with wiggles, is that the two signals need to be recieved having exactly the same transmission delay along whatever path they individually take (in addition to that path being 'impedance matched!') so that the transitions arrive at the same time too.
They are received as a differential signal, but they're usually sent as two normal digital output signals (maybe with differnent voltage levels) that just happen to be synchronously clocked at the same time.
Doing this gives two major benefits, and was sort of a quantum leap in digital technology, as well. The first benefit is that the reception is quite good at rejecting a common-mode (same disruption to both sides of the pair) interference signal, whether it's electrostatic or electromagnetic.
But the second, lesser-known benefit, is that by passing both wires more-or-less through the same region of space (ie, keeping them fairly close to each other) when the logic state switches, it doesn't cause a disruption to the total current down the pair.
This is because, each of the two signals being a 'normal, single ended logic' (aka, DC between two levels, current changes with levels but is always flows in the same direction) signal, the total current down the pair becomes a constant so long as they always swap states (low voltage and current, high voltage and current) at the same time. This means the total current down the physical space the pair follows is mostly just constant DC, regardless of the logic activity. And THIS property, means that the pair does NOT emit it's own electro-magnetic radiation. If you like, the change in current on one wire, is cancelled out by the change of current next to it in the other wire, both changes move down the pair at the group velocity, and all wires that arn't between the two (which is all of them, notice!) therefore don't 'see' any net change in current. Therefore, no interference is emitted, **even when the changes are happening so fast that the pair length would otherwise be long enough to act as an antenna**.
So, there you go - by making a pair of signals always switch at the same time, and also making each be 'impedance matched' (just stops resonance from the pulses bouncing back and forth and building up a standing wave), we can send data very fast beween two points, without the pair acting as an antenna and emitting a radio signal which would interfere with other circuits.
This is usually used in conjunction with differential reception (better immunity to ALL other possible interference), but you can still use it even if the receiver is 'single ended'. What you do is put a 'load matching' resistance at the end of the complement signal that you're 'not using', and place that right nearby the pin that is receiving the signal that you are using (that 'dummy' load should be tuned to 'look' just like the equivalent resistance the single-ended chip receving the digital signal has, so the currents remain balanced at all times).
Had people known about this back in the 80's, we'd have had much faster PC's originally. Many of the old-school 'high speed' MSI logic chips were limited by interference between parallel wires that they didn't, at the time, have a solution for, and this is that solution. They tended to be limited to low MHz, when their chips were already theoretically capable of 100's MHz, they just couldn't get them to run without immediately crashing due to the interference of non-impedance-matched traces acting like little antennas, ringing with resonance, and inducing interference in all nearby other traces.
What a mess that was! And on top of that, they had 'ground bounce' which was causing the receiving chips to compare the incoming signal to a bad 'zero' reference which was anything but. On top of *all that*, complementory logic means the IO current for a chip using only it, has a constant current draw from the power supply, as the use of current is constant regardless of the logic states of the outputs. Guess what *wasn't* true back in those days? You guessed it - the power supply draw depended on the logic state of the output pins of the chip, so the logic activity modulated the power supply draw, causing the power supply to have noise on it too.
So, once it was realized that complementory logic gets rid of all of these problems. It was 'discovered' that we could then use a much smaller voltage swing too - and further reduce noise, without losing reliabilty, and gain more energy efficiency at the same time. So that's why LVDS is the way it is.
The final 'nail on the coffin' that lead to the amazing utility of PCIe, was the 8b/10b encoding scheme to insert the clock into the same pair as the data, so the receiver need only have the one logic signal to accurately and reliably figure out when to sample it. This is why both sides of the PCIe lane are totally independant - because there's no use clocking your reception of the RX signal at the same time you do the TX signal, especially if you don't actually know how long a delay it is to the other end of the link. And trying to fix the 'delay' by just sending the clock independantly - well, that's how SDRAM (including DDRx and LPDDRx) all still works: you have to send a copy of the clock along with the signals in each direction, so that the receiver can use *that* clock to properly receive the data. 8b/10b encoding does away with all of that.
And so yeah, throw in a little housekeeping around auto-tuning the link (and auto-inverting the signal too!), and allowing transparent link-agglomeration (which is good for fault-tolerance also more bandwidth, and why a X16 card still works over X1) all automatically at the digital hardware level, and you have PCIe the way we know it. Sprinkle just a little protocol on top, for arranging DMA transfers directly to/from the memory controller, so as not to thrash the CPU with interrupts, (and while you're at it, add a way to do interrupts, too, for legacy PCI support) and you're basically there.
But those little pairs of inline SMD parts are definitely resistors - probably in the range 20 to 90. Because PCIe *isn't* AC, and if you 'use' the source resistance of the chip, you can just supplement it with a little extra series resistance to make an impedance match which just causes the reflected-back signals to get absorbed, without having to have an L-pad, resistive divider, or transformer that you'd need to make the impedance match work in both directions. This usually means the receiver doesn't bother with an impedance match, because those resistors will do a good-enough job of catching the reflection and preventing them from re-reflecting back in the same direction as the data is flowing. This is 'good enough', to an engineer, often the very best kind of 'good'.
MIND-BENDINGLY EYE-OPENING!!!!! lol
I was having a REALLY hard time seeing the things you were pointing out... I had to either increase or decrease my video cards video brightness (it only adjust the brightness of video playback, and not the rest of the screen or 3d rendered stuff like games!! I just discovered it on my AMD 6650XT in the AMD Adrenaline app under Audio & Video... it's been useful and I'm telling everyone about it lol) I was able to adjust it and see everything really well, but it would have been impossible to watch this without making any adjustments.....
I wonder if this has to do with the YT stream, or my TV's settings (yes I'm using a 50" 4K TV as my computer screen.... but I sit about 7 feet away lol) .. I think it's the stream because everything else looks great, but I am CONSTANTLY having to adjust it when I watch UA-cam... which I do pretty much 24/7 lol ..... - I wonder if everyone else was able to see the different parts you pointed out just fine.... hrmmm I think HDR also has to do with this too.... which I have turned on in Windows
- Maybe I should watch it again on my actual computer monitor... it's only 34" 1440p but it's got a 165hz refresh rate.. but I never use it really....
- - -Why am I tell you all this?? i have no idea!! LOL That was a really cool video tho Jeff!!! THANK YOU!!! :D
Good suggestions-honestly, I probably over-exposed the images a little bit (but I tried to bring out some of the darker details while preserving some highlights too, since many traces are so faint).
But it's a tradeoff-since most of our displays are okay-ish at HDR, and I target all screens, I try to cram as much of the image data in there as possible. The raw TIFF files I got from the scanner contain a bit more detail.
You sure you haven't got a silly setting turned on? My samsung 4k monitor has a "eye saver" mode and screws all the colours up. Screws me around every time.