Please do hit the like button if this video helped That keeps me motivated :) You can give your Mock Interview @Topmate - topmate.io/ani... Connect with me at LinkedIN - / sahaanish Thank You :)
Join Our Telegram Group : t.me/All_About_Learning Visit Our Website - prepfusion.in/ for Comprehensive courses Watch my Honest GATE story here - ua-cam.com/video/HAM9y_2rD0w/v-deo.htmlsi=lB_rSPVlslA0iMs4 Book your mock Interview - topmate.io/anish_saha/495015 You can watch Himanshu taking my Mock Interview here - ua-cam.com/video/S66fM8N-q0c/v-deo.html Please don't forget to like the video if you want more videos like this!❤
The two inductor and resistor question the current at t=0+ is wrong. Think why? Hint: check KVL at t=0+ Also in the last question slope in triode region will be more. Think on it.
Being graduated from Shibpur, Nice to see both of you, one coming from Shibpur & another from Jadavpur University grad making VLSI easier 😊 to aspirants.
@ 21:17 Could you please explain a bit how this equation was formed? L1*I + 0 = (L1+L2) * I(0+) Is this KVL? From my knowledge, the voltage across the inductor is L*dI/dt . What is the L*I quantity in the equation from the video?
V=d(flux)/dt => flux=Vu(t)=LI => I=V/L{u(t)}. Therefore can I replace the impulse voltage source by a constant current source at t=0+? Then the constant current of V/L will flow through the first inductor and through the register and after sometime Vo will become zero as the second inductor will be shorted (no current through register) , entire current through the both of the inductors( shorted path). If I am wrong please correct me .
@25:26 , isn't that a common-source instead of a common-drain(source follower)? The PMOS input is the gate, output is the drain , and the source terminal is common. If so, I thought there would be a 180 degree shift due to CS topology. As a result, the A terminal should be positive and B terminal should be negative. Please let me know if I am missing some concept here.
I see. So the output of PMOS "appears" to be on source terminal since that is where we are taking the feedback from. Which is why it can be considered as common drain.
In the second question, because there is a resistor in parallel to two inductors, Why the current is settling to a finite value in inductor? Shouldn't it go to zero because all the energy is lost through the resistor?May you explain it ?
Thanks a lot for this video! @14:24, I am trying to understand how the current through inductor settles at V/2L and not 0 amps at steady state. If V itself is 0 at steady state, then the V/2L quantity (i.e current through inductor at steady state) should also be 0 right? Please do correct me if I am missing something.
At 7:05 you asked what is the dc gain. Can I find it in this way, first derive the transfer function then put S=0 and get dc gain.Just in the same way you mentioned in one of your videos.Will the interviewer allow me to do so ?
Join Our Telegram Group : t.me/All_About_Learning
Visit Our Website - prepfusion.in/ for Comprehensive courses
Watch my Honest GATE story here - ua-cam.com/video/HAM9y_2rD0w/v-deo.htmlsi=lB_rSPVlslA0iMs4
Book your mock Interview - topmate.io/anish_saha/495015
You can watch Himanshu taking my Mock Interview here - ua-cam.com/video/S66fM8N-q0c/v-deo.html
Please don't forget to like the video if you want more videos like this!❤
The two inductor and resistor question the current at t=0+ is wrong. Think why?
Hint: check KVL at t=0+
Also in the last question slope in triode region will be more. Think on it.
Being graduated from Shibpur, Nice to see both of you, one coming from Shibpur & another from Jadavpur University grad making VLSI easier 😊 to aspirants.
Thanks Dada. Means a lot :-)
Thankyou Dada ♥️
big ups bhai... carry on.
Being a TI aspirant myself, this video was a need of the hour. Thanks Anish da and Himanshu bhaiya. ❤
@ 21:17 Could you please explain a bit how this equation was formed? L1*I + 0 = (L1+L2) * I(0+)
Is this KVL? From my knowledge, the voltage across the inductor is L*dI/dt . What is the L*I quantity in the equation from the video?
That is Flux
V=d(flux)/dt => flux=Vu(t)=LI => I=V/L{u(t)}. Therefore can I replace the impulse voltage source by a constant current source at t=0+? Then the constant current of V/L will flow through the first inductor and through the register and after sometime Vo will become zero as the second inductor will be shorted (no current through register) , entire current through the both of the inductors( shorted path). If I am wrong please correct me .
Please mention the time
thank you soo much guys
@25:26 , isn't that a common-source instead of a common-drain(source follower)?
The PMOS input is the gate, output is the drain , and the source terminal is common. If so, I thought there would be a 180 degree shift due to CS topology. As a result, the A terminal should be positive and B terminal should be negative.
Please let me know if I am missing some concept here.
See what is the input to the mos and what output feedback we are taking. Don't just look at Vo and Vi blindly.
I see. So the output of PMOS "appears" to be on source terminal since that is where we are taking the feedback from. Which is why it can be considered as common drain.
👍🏻👍🏻👍🏻
In the second question, because there is a resistor in parallel to two inductors, Why the current is settling to a finite value in inductor? Shouldn't it go to zero because all the energy is lost through the resistor?May you explain it ?
One of the inductor is energizing and other is denergizing at some stage current will become same through both of them.
Sir , I am not understanding @14:21 how it is V/2L?
18:35 please explain how average value you found?
Compute the area of the graph and divide by time period you will get average value
Thanks a lot for this video! @14:24, I am trying to understand how the current through inductor settles at V/2L and not 0 amps at steady state. If V itself is 0 at steady state, then the V/2L quantity (i.e current through inductor at steady state) should also be 0 right? Please do correct me if I am missing something.
V and Vo are two different things V was the area of the impulse and the voltage across the inductor goes to zero.
Got it. Thanks!
At 7:05 you asked what is the dc gain. Can I find it in this way, first derive the transfer function then put S=0 and get dc gain.Just in the same way you mentioned in one of your videos.Will the interviewer allow me to do so ?
No no you directly find DC gain without transfer function
Sir in youtube where can I get best playlist for gate network analysis
Watch my gate roadmap video