Greatly helped me for visualising my outputs of hardware accelerator I made for image processing for my mtech project. Thank you for the clear and precise explanation.
I really thank your kind explanation and files in git. I tried another web sites code, but vga didnt work because of different frequency or resolutions. Your codes helped me revise my mistake. (afraid my poor english, hope to understand)
Hi. Forgive me if I am being presumptuous. In order to make this work you need more that just the xdc file. You must add the Verilog files as source files and add the xdc file as a constraint file. Then, run synthesis, run implementation, and generate the bitstream.
Can you make cpld board altera max ii with atmega328 spi communication extended io pins input output video verilog code & schematic give code in description. I am your subscriber i am waiting for your video on this topic.
Hi David - Another very interesting & informative video - Thanks again for putting all your FPGA Videos "out there" - Cheers :)
Thank you for the feedback. I'm glad my videos are helpful and useful to people. Thanks for letting me know.
Greatly helped me for visualising my outputs of hardware accelerator I made for image processing for my mtech project. Thank you for the clear and precise explanation.
Thank you for the positive feedback. I'm so glad that it was helpful to you.
You are doing a great job! 👌🙌
Thank you for the encouragement.
I really thank your kind explanation and files in git.
I tried another web sites code, but vga didnt work because of different frequency or resolutions. Your codes helped me revise
my mistake. (afraid my poor english, hope to understand)
I understand. Thanks for your comments. I am glad that my videos are helpful to someone.
Quite helpful and explaintory. Thank you so much.
After giving the xdc file in vivado, the bit stream isn't generating. What should i do?
Hi. Forgive me if I am being presumptuous. In order to make this work you need more that just the xdc file. You must add the Verilog files as source files and add the xdc file as a constraint file. Then, run synthesis, run implementation, and generate the bitstream.
Can you share the code please? Thanks
There is a link in the description.
Can you make cpld board altera max ii with atmega328 spi communication extended io pins input output video verilog code & schematic give code in description. I am your subscriber i am waiting for your video on this topic.