Cadence - How to find device capacitance

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  • Опубліковано 16 січ 2025

КОМЕНТАРІ • 9

  • @its_aleix
    @its_aleix 15 днів тому

    Thanks for your explanation,but I have a question about the sp simulation vs dc simulation when I used mos as a constant cap(connect body、drain and source,just measure gate to ground cap),I found the dc simulation absolutely different from sp simulation。 The curve tends to go in the opposite direction。 had no clue,In the end, which way can accurately measure the mos capacitor I use in the loop_filter circuit situation???

  • @becermis
    @becermis 11 місяців тому

    Great content. Thanks!

  • @kirin9987
    @kirin9987 Рік тому

    Thank you for your kind explanation. I wonder why the dc simulation result is so different from the s parameter sim. Can you give me your opinion?

    • @wallingphd
      @wallingphd  Рік тому +1

      The DC simulation is just based on the device model, but does not include estimates of metal capacitance due to layout parasitics. You can add a few more terms (e.g., Coverlap, Cjs, etc.) to get a closer approximation, but the safest bet is to just use the SP.

    • @kirin9987
      @kirin9987 Рік тому

      @@wallingphd thank you!

  • @pablomarco5118
    @pablomarco5118 5 місяців тому

    Many thanks prof!

  • @mensh__
    @mensh__ Рік тому

    I think the xval function with the psp sim would return -1 to 1 GHz. So, you should add the pss freq to that.

    • @wallingphd
      @wallingphd  Рік тому

      The susceptance is linearly increasing with frequency, and the value in the plot is the correct value at the offset. Hence, we should not add the pss frequency to it. You can verify by setting the PSP frequency range to absolute and sweeping from frf +/- offset (e.g., 4.6GHz to 6.6GHz in this case). The result will be the same, albeit there will not be a divide by 0 in the middle of the range.

  • @yabiliao8779
    @yabiliao8779 9 місяців тому

    thanks!