sta lec21 hold timing fixes in path part2 | Static Timing Analysis tutorial | VLSI

[@lanlin8392]

To calculate RT, why we need add library hold time and clock uncertainty instead of decrease them as setup time check do? Could you please help to explain that? Thank you.

[@amedheka]

Tarrival should be 0.8ns ?

[@merrygo7189]

What are the methods we can apply during PNR stage for hold fixation...?

[@saidileepchowdarynuthalapa6364]

In a synchronous clock system if there is a clock uncertainty it should be considered for both RT and AT right? but why only in the RT in the above example?

[@saidileepchowdarynuthalapa6364]

@@VLSIAcademyhub thanks for that explanation. got it

[@quest95112]

@@saidileepchowdarynuthalapa6364 what is the explanation? can you share please? thanks

[@suryanshraheja9990]

Hello sir....could not understand uncertainty here you have said it is taken 0 but in report it is clearly showing 60 ps plz elaborate

[@lanlin8392]

same question, could you explain that, thanks a lot.

[@mekalagowthami162]

Hold salck is AT-RT but in timing report, Why it is like RT-AT....?
plz give clarity on this sir...

[@alekhyarao4402]

what are the hold fixes in post route

[@alekhyarao4402]

@@VLSIAcademyhub Thank you sir

[@hemamalini6195]

Can u tell what is the explanation?

[@luckeylokesh1952]

Slack is tr- ra

[@Problem_Solut1ons]

@ 04:57 The T(uncertainty) = 60ps written