I understand why it is better to do the matching before the other trace returns to the same layer -- that way, the final portion of the trace is matched, and subject to the same/offsetting interference. But what is the argument for putting the length matching near the driver, instead of after the via (where they are separated anyhow)?
Hi Jim, nice to see you around again! THis is another really good question so I'll do it in our filming session today. In short, the idea is that any common mode noise picked up between the driver and receiver is in-phase and does not experience mode conversion at the load end of the line.
@@Zachariah-Peterson This makes more sense to me than it did 2 months ago ... I *think* you're saying that length matching (anywhere) gets both half-signals there at the same time, but from the mismatch until the makeup, it is really just two unrelated traces instead of a differential pair. The reason not to wait until after the via is that the original length difference is usually closer to the driver. (And I'm assuming the question got dropped in editing, or else I just missed it ... unless you have a *really* long lead time.)
@@jimjjewett With vias that's how I've usually managed to do it, whether it's coming out of/into a BGA breakout or coming out of/into a connector. Also my lead time right now is worse than Texas Instruments'...
First of all thank you very much for these excellent videos. Please explain more about when do we need length matching and how can I precisely calculate the length?
Length matching is needed when there is too much timing mismatch between two ends of a differential pair, or when there is timing mismatch between multiple signals in a parallel bus. The idea is to bring the timing of the signals back into alignment by adding some length to some of the traces, this way you keep all the signals synchronized within some timing window. It is generally needed with differential signals that have fast edge rates, as well as in fast parallel buses like DDR. It is also needed in some cascaded RF systems that use single-ended traces, but that is more of an advanced topic and it is used to synchronize transceivers to the same clock.
@@Zachariah-Peterson Thank you for answering my question. If I need length matching, length of a route must less equal than turn into critical length of a transmission line? If L sub R is more than critical length of a transmission line, I have to impedance matching for example 50 ohms in "impedance profile in Altium Designer"?
I didn't quite understand one thing. Please tell me, if the resulting propagation delay is 138.27ps/in, then why in the example the length of the conductors on the printed circuit board was used longer than one inch? Wouldn't that create a total(138.27ps X conductor length) latency substantially greater than 150 (for SN65LV1023A) picoseconds?
The length of the traces only determines the amount of time the signal needs to travel between the two components, it does not matter for length matching. Only the rise time matters for length matching and that specification is used regardless of the length of the traces. So your traces could be 20 inches long (like in a large backplane) and the length mismatch tolerance would still only be based on the rise time. It may turn out that if your traces are very short, then the allowed mismatch is longer than your trace length. So just worry about the calculated mismatch length, the trace length does not matter for calculating this constraint.
Impedance is not to do with the length, it's all about the material and the trace width and gnd clearance(if the coplanar waveguide is used) so, if you don't change the trace width or the gnd clearance then impedance will not be affected seriously.
A mismatch can cause issues in the time domain, which will turn into signal issues in the phase domain (jitter). Zach has other good videos about differential tuning that can answer this question better. :-)
Technically the differential impedance is different in that region where there is mismatch, but it only matters for input impedance in certain cases where rise time is very fast. This is because in the mismatched region, a portion of the transmission line does not have its electric field terminated at the nearby opposite polarity trace, so there could be an input impedance deviation right at that point. Whether you actually notice the input impednace deviation depends on the length of the mismatch and the rise time. Most people will start to make a comparison between the signal velocity and the mismatch length to figure out if there is some reflections or something. In my opinion, you should use the bitstream's Nyquist frequency to figure out if the impedance mismatch in that area really matters. This is a really good question so I'll look at it in our next film session.
Don't you think that calling this feature a "length matching" is a bit of a misnomer because the actual goal is to match delays, and not just physical length? Once upon a time matching length was "good enough" to match delays "close enough", but nowadays with GHz buses becoming a routine as opposed to something out of ordinary, matching length of traces on different layers can get you in trouble, as difference in signal propagation speed will lead to delays mismatch, which can become significant enough to cause problems. Also I think Altium needs to update AD to auto-calculate via delays - since AD already know all relevant geometry details via stackup, it shouldn't be that difficult, also those delays will be different depending on which layer signal travels from/to.
Yes I do think it is a misnomer, but unfortunately the SEO gods at Google force us to still use the term because everyone else continues to use it. And with via delays I agree with you, but I think the problem is getting licensed a good calculator that can do the auto calculation quickly for your via design rules or live in the design. The problem is that if you have it running in the DRC engine, then it would constantly run the via delay calculation every time you moved something near the via, or if you moved/resized the via. If the model is slow then you would get a big lag in program performance. They could set it up to run in your DRCs manually, that's probably the best bet/safest way to do it. Otherwise, you would have to create a via profile and enforce that as a design rule, just like it works with an impedance profile.
@@Zachariah-Peterson Well even quick & dirty method would be better than none at all. Right now I don't think it's even possible to specify different via delays for different layer pairs, only a single delay which kind of makes this setting useless for practical purposes - unless it's a blind or buried via which only connects a single pair of signal layers.
I just checked on one of my designs and I did not see those options greyed out. That was for matching on DDR, but you can still select those options once you click on the single-ended length matching tool. If you're in the middle of using the length matching utility and you hit tab to pause the tool, then it will grey out the buttons so that you can't switch between different styles mid-route.
In order for a differential interface to function (meaning you can retreive data), you do not need to mount the traces right next to each other, and you don't even need to route them on the same layer. As long as the individual trace impedances are correct and as long as the signals on each trace arrive within the correct time window, the interface will function correctly. The only reason to keep the traces very close together is for reduction of radiated emissions when ground is far from the traces and to set the trace width to a small value. When the dielectric layer is thin and ground is adjacent then the traces can have greater separation from each other.
Are you SURE that length only does length matching on the top layer? That doesn't make any sense that someone would have designed it to intentionally work that way. More importantly, what you are matching here, since you are matching between the _P and _N of a single differential pair, is typically called phase tolerance. That should be matched along the entire length, not just in one spot. It needs to have length added to one side of the pair anywhere along the pair that the length is out of phase tolerance. If you don't match along the entire length of the differential pair, the _P and _N "legs" wave front can be skewed more than the set tolerance. That defeats the common mode noise rejection, an important feature of using differential pairs. It's also odd that Altium treats differential pair phase tolerance as any other length match. It's something that should, IMO, just be set in the differential pair setup. It appears to also mean you have to set it up for every single differential pair, since each pair can have a different overall length, even if they are in a true length match group, as that group will have a much higher tolerance (like hundreds of mills) than the length matching for phase tolerance (which can be around 10-25 mils). Is there is a way to set this phase tolerance "length match" to either all differential pairs or a group of differential pairs, knowing that the pairs may also be part of another length matching group? In other tools, that's the reason it's typically handled as two distinct functions.
I don't recall saying that the tool only operates on the top layer or that you should only do it on the top layer. Length tuning can be performed in any layer. You can even route the signals in two different layers with two different propagation constants and do length tuning in the faster layer so that you restore the edge rate timing you see at the receiver, you just won't get all the noise cancellation benefits of differential pairs and there will probably be some mode conversion. I've never simulated that last point so don't quote me on it but that is what happens when you have asymmetry along the propagation path. As far as where you match, typically that would happen when coming out of a connector or driver component because that is where the asymmetry could arise, but it could also arise whenever you make a turn and you would add a small jut in the shorter trace to lengthen it slightly and re-match the phases. This makes a very slight impedance discontinuity that you might notice in very broad bandwidths. I actually show examples of this in another video. And there is no matching "along the entire length of the pair", that makes no sense. If I have two traces that are skewed by 10 mils, then I only need to apply 10 mils, it doesn't matter if the resultant length of that net is 1 inch or 10 inches. Also there is a design rule for length tuning or delay tuning in AD, it's in the rules editor in the same window, you can set the length or delay value, whichever suits your needs, but you need to set up an impedance profile for those nets to get accurate delay tuning. The reason we don't use the term "phase matching" for digital signals is because the phase is not well-defined, the phase is actually a spectrum. In a perfect world the phase difference is a linear function of frequency, but once you have skew between two differential pairs that phase difference is not constant because the propagation constant can change in that region with skew. That is exactly why you have mode conversion that becomes prominent at high frequencies. And yes there is a delay within a group option as well as a delay within a pair option. You can set up both for diff pair nets.
@@Zachariah-Peterson I re-listened to the video starting at 8:30, thru the end of the high-speed matched length setup explanation. You may wan to re-listen to that, and pay attention to what you say about the top layer, using length vs delay. It certainly caused me to tilt my head and go "huh?" a few times. "And there is no matching "along the entire length of the pair", that makes no sense." It has to make sense (unless we're misunderstanding each other), otherwise, you don't have the desired common mode noise rejection. You can't have a phase tolerance spec of say 25 mils, and have a length difference of 500 mils halfway through the routing, and then add 500 mils in one place. The wave fronts would obviously be skewed by more than the tolerance. It is important to do phase tolerance length matching along the entirety of a differential pair, where ever the two legs are out of phase by the tolerance specified, you add a "bump". It's also called "dynamic phase tolerance". Differential phase tolerance has been really well defined in the PCB industry for many decades. I don't see the significance of "phase is a spectrum" WRT differential phase tolerance and adjusting for that in PCB traces so the wave fronts in both legs in a differential pair travel coincident within tolerance from transmitter to receiver. This is physical length matching if the two legs of a single differential pair we're talking about, with two legs having exactly the same physical propagation characteristics, no matter what the frequencies or spectrum. Though it is true that there can be different propagation delay on different layers (there also is on the same layer depending on the weave, epoxy etc.), it's really not significant at anything under even 6G (in general, depends on the signaling) and a length match by actual length should be fine. There certainly is nothing wrong with doing it by delay, providing the delay is actually calculated correctly. Does Altium calculate the delay based on frequency? I still haven't been able to figure out how to put multiple differential pairs into a single group to do ONLY phase tolerance between the two legs of each differential pair. Thank you for the reply, and the videos!
I'm actually surprised that a tool that knows every theoretical parameter of a design, down to layer thicknesses and dielectric constants, can't auto-check via propagation delays, your tool literally knows if a via is a stub as well as things like if via rings are enabled on a per layer basis. Apply that information! External calculations with incorrect information or a design that simply changes later, are going to cause errors there.. Also whoever is managing this channel, you need to enable embedded playback.. we can't watch SOME of your playlisted tutorial videos from INSIDE your software player. "Snapping When Creating Polygons" being the first of many I've already encountered.. plays on site fine, but in your software, broken.. 'An error occurred. Please try again later.' This means you randomly have 'embedded playback' blocked on a bunch of your own support videos that you guide new users to. 🤦
The problem with via delay is that it is not so simple to calculate, there is no closed form solution and it depends on several factors to get correct. There is a model from Howard Johnson's textbook that many calculators will incorporate, but that model is grossly incorrect and Howard Johnson even says in his textbook that his model is incorrect, so if you ever see someone provide a via delay calculator it is most likely wrong. I am surprised at the number of people that point to this model from Johnson's textbook, and yet they fail to look forward 2 pages in the textbook to see where Johnson explains how and why it is incorrect. I've done videos on this topic and have pointed out many times how these calculators which purport to give this information are incorrect.
Thank you very much. Your Videos are very helpful and informative.
Best explanation btw! 👍🏼👍🏼👍🏼👍🏼👍🏼👍🏼👍🏼
Glad you think so!
very useful
I understand why it is better to do the matching before the other trace returns to the same layer -- that way, the final portion of the trace is matched, and subject to the same/offsetting interference. But what is the argument for putting the length matching near the driver, instead of after the via (where they are separated anyhow)?
Hi Jim, nice to see you around again! THis is another really good question so I'll do it in our filming session today. In short, the idea is that any common mode noise picked up between the driver and receiver is in-phase and does not experience mode conversion at the load end of the line.
@@Zachariah-Peterson This makes more sense to me than it did 2 months ago ... I *think* you're saying that length matching (anywhere) gets both half-signals there at the same time, but from the mismatch until the makeup, it is really just two unrelated traces instead of a differential pair. The reason not to wait until after the via is that the original length difference is usually closer to the driver. (And I'm assuming the question got dropped in editing, or else I just missed it ... unless you have a *really* long lead time.)
@@jimjjewett With vias that's how I've usually managed to do it, whether it's coming out of/into a BGA breakout or coming out of/into a connector. Also my lead time right now is worse than Texas Instruments'...
Thanks a lot ❤
First of all thank you very much for these excellent videos. Please explain more about when do we need length matching and how can I precisely calculate the length?
Length matching is needed when there is too much timing mismatch between two ends of a differential pair, or when there is timing mismatch between multiple signals in a parallel bus. The idea is to bring the timing of the signals back into alignment by adding some length to some of the traces, this way you keep all the signals synchronized within some timing window. It is generally needed with differential signals that have fast edge rates, as well as in fast parallel buses like DDR. It is also needed in some cascaded RF systems that use single-ended traces, but that is more of an advanced topic and it is used to synchronize transceivers to the same clock.
@@Zachariah-Peterson Thank you for answering my question. If I need length matching, length of a route must less equal than turn into critical length of a transmission line? If L sub R is more than critical length of a transmission line, I have to impedance matching for example 50 ohms in "impedance profile in Altium Designer"?
Dear Sir, Please upload videos regarding How to choose design rules values
I didn't quite understand one thing. Please tell me, if the resulting propagation delay is 138.27ps/in, then why in the example the length of the conductors on the printed circuit board was used longer than one inch? Wouldn't that create a total(138.27ps X conductor length) latency substantially greater than 150 (for SN65LV1023A) picoseconds?
The length of the traces only determines the amount of time the signal needs to travel between the two components, it does not matter for length matching. Only the rise time matters for length matching and that specification is used regardless of the length of the traces. So your traces could be 20 inches long (like in a large backplane) and the length mismatch tolerance would still only be based on the rise time.
It may turn out that if your traces are very short, then the allowed mismatch is longer than your trace length. So just worry about the calculated mismatch length, the trace length does not matter for calculating this constraint.
@@Zachariah-Peterson Now I understand. Thanks a lot Zach.
Does too much length mismatch creates impedance discontinuity for differential pair?
Impedance is not to do with the length, it's all about the material and the trace width and gnd clearance(if the coplanar waveguide is used)
so, if you don't change the trace width or the gnd clearance then impedance will not be affected seriously.
A mismatch can cause issues in the time domain, which will turn into signal issues in the phase domain (jitter). Zach has other good videos about differential tuning that can answer this question better. :-)
Technically the differential impedance is different in that region where there is mismatch, but it only matters for input impedance in certain cases where rise time is very fast. This is because in the mismatched region, a portion of the transmission line does not have its electric field terminated at the nearby opposite polarity trace, so there could be an input impedance deviation right at that point. Whether you actually notice the input impednace deviation depends on the length of the mismatch and the rise time. Most people will start to make a comparison between the signal velocity and the mismatch length to figure out if there is some reflections or something. In my opinion, you should use the bitstream's Nyquist frequency to figure out if the impedance mismatch in that area really matters.
This is a really good question so I'll look at it in our next film session.
Don't you think that calling this feature a "length matching" is a bit of a misnomer because the actual goal is to match delays, and not just physical length? Once upon a time matching length was "good enough" to match delays "close enough", but nowadays with GHz buses becoming a routine as opposed to something out of ordinary, matching length of traces on different layers can get you in trouble, as difference in signal propagation speed will lead to delays mismatch, which can become significant enough to cause problems. Also I think Altium needs to update AD to auto-calculate via delays - since AD already know all relevant geometry details via stackup, it shouldn't be that difficult, also those delays will be different depending on which layer signal travels from/to.
Yes I do think it is a misnomer, but unfortunately the SEO gods at Google force us to still use the term because everyone else continues to use it. And with via delays I agree with you, but I think the problem is getting licensed a good calculator that can do the auto calculation quickly for your via design rules or live in the design. The problem is that if you have it running in the DRC engine, then it would constantly run the via delay calculation every time you moved something near the via, or if you moved/resized the via. If the model is slow then you would get a big lag in program performance. They could set it up to run in your DRCs manually, that's probably the best bet/safest way to do it. Otherwise, you would have to create a via profile and enforce that as a design rule, just like it works with an impedance profile.
@@Zachariah-Peterson Well even quick & dirty method would be better than none at all. Right now I don't think it's even possible to specify different via delays for different layer pairs, only a single delay which kind of makes this setting useless for practical purposes - unless it's a blind or buried via which only connects a single pair of signal layers.
@@asmi06 what do you mean?
Quick question - when length matching in Altium, why is Trombone / Sawtooth options greyed out? I can only length match using the Accordion option.
I just checked on one of my designs and I did not see those options greyed out. That was for matching on DDR, but you can still select those options once you click on the single-ended length matching tool. If you're in the middle of using the length matching utility and you hit tab to pause the tool, then it will grey out the buttons so that you can't switch between different styles mid-route.
@@Zachariah-Peterson ahhhhh that was my issue. Attempting to switch while I had already started the tool. Thanks!
14:00 Won't high speed differential pairs have issues when routed like this?
In order for a differential interface to function (meaning you can retreive data), you do not need to mount the traces right next to each other, and you don't even need to route them on the same layer. As long as the individual trace impedances are correct and as long as the signals on each trace arrive within the correct time window, the interface will function correctly. The only reason to keep the traces very close together is for reduction of radiated emissions when ground is far from the traces and to set the trace width to a small value. When the dielectric layer is thin and ground is adjacent then the traces can have greater separation from each other.
Are you SURE that length only does length matching on the top layer? That doesn't make any sense that someone would have designed it to intentionally work that way. More importantly, what you are matching here, since you are matching between the _P and _N of a single differential pair, is typically called phase tolerance. That should be matched along the entire length, not just in one spot. It needs to have length added to one side of the pair anywhere along the pair that the length is out of phase tolerance. If you don't match along the entire length of the differential pair, the _P and _N "legs" wave front can be skewed more than the set tolerance. That defeats the common mode noise rejection, an important feature of using differential pairs. It's also odd that Altium treats differential pair phase tolerance as any other length match. It's something that should, IMO, just be set in the differential pair setup. It appears to also mean you have to set it up for every single differential pair, since each pair can have a different overall length, even if they are in a true length match group, as that group will have a much higher tolerance (like hundreds of mills) than the length matching for phase tolerance (which can be around 10-25 mils). Is there is a way to set this phase tolerance "length match" to either all differential pairs or a group of differential pairs, knowing that the pairs may also be part of another length matching group? In other tools, that's the reason it's typically handled as two distinct functions.
I don't recall saying that the tool only operates on the top layer or that you should only do it on the top layer. Length tuning can be performed in any layer. You can even route the signals in two different layers with two different propagation constants and do length tuning in the faster layer so that you restore the edge rate timing you see at the receiver, you just won't get all the noise cancellation benefits of differential pairs and there will probably be some mode conversion. I've never simulated that last point so don't quote me on it but that is what happens when you have asymmetry along the propagation path. As far as where you match, typically that would happen when coming out of a connector or driver component because that is where the asymmetry could arise, but it could also arise whenever you make a turn and you would add a small jut in the shorter trace to lengthen it slightly and re-match the phases. This makes a very slight impedance discontinuity that you might notice in very broad bandwidths. I actually show examples of this in another video. And there is no matching "along the entire length of the pair", that makes no sense. If I have two traces that are skewed by 10 mils, then I only need to apply 10 mils, it doesn't matter if the resultant length of that net is 1 inch or 10 inches.
Also there is a design rule for length tuning or delay tuning in AD, it's in the rules editor in the same window, you can set the length or delay value, whichever suits your needs, but you need to set up an impedance profile for those nets to get accurate delay tuning. The reason we don't use the term "phase matching" for digital signals is because the phase is not well-defined, the phase is actually a spectrum. In a perfect world the phase difference is a linear function of frequency, but once you have skew between two differential pairs that phase difference is not constant because the propagation constant can change in that region with skew. That is exactly why you have mode conversion that becomes prominent at high frequencies.
And yes there is a delay within a group option as well as a delay within a pair option. You can set up both for diff pair nets.
@@Zachariah-Peterson I re-listened to the video starting at 8:30, thru the end of the high-speed matched length setup explanation. You may wan to re-listen to that, and pay attention to what you say about the top layer, using length vs delay. It certainly caused me to tilt my head and go "huh?" a few times.
"And there is no matching "along the entire length of the pair", that makes no sense." It has to make sense (unless we're misunderstanding each other), otherwise, you don't have the desired common mode noise rejection. You can't have a phase tolerance spec of say 25 mils, and have a length difference of 500 mils halfway through the routing, and then add 500 mils in one place. The wave fronts would obviously be skewed by more than the tolerance. It is important to do phase tolerance length matching along the entirety of a differential pair, where ever the two legs are out of phase by the tolerance specified, you add a "bump". It's also called "dynamic phase tolerance". Differential phase tolerance has been really well defined in the PCB industry for many decades. I don't see the significance of "phase is a spectrum" WRT differential phase tolerance and adjusting for that in PCB traces so the wave fronts in both legs in a differential pair travel coincident within tolerance from transmitter to receiver. This is physical length matching if the two legs of a single differential pair we're talking about, with two legs having exactly the same physical propagation characteristics, no matter what the frequencies or spectrum.
Though it is true that there can be different propagation delay on different layers (there also is on the same layer depending on the weave, epoxy etc.), it's really not significant at anything under even 6G (in general, depends on the signaling) and a length match by actual length should be fine. There certainly is nothing wrong with doing it by delay, providing the delay is actually calculated correctly. Does Altium calculate the delay based on frequency?
I still haven't been able to figure out how to put multiple differential pairs into a single group to do ONLY phase tolerance between the two legs of each differential pair.
Thank you for the reply, and the videos!
I'm actually surprised that a tool that knows every theoretical parameter of a design, down to layer thicknesses and dielectric constants, can't auto-check via propagation delays, your tool literally knows if a via is a stub as well as things like if via rings are enabled on a per layer basis. Apply that information! External calculations with incorrect information or a design that simply changes later, are going to cause errors there..
Also whoever is managing this channel, you need to enable embedded playback.. we can't watch SOME of your playlisted tutorial videos from INSIDE your software player. "Snapping When Creating Polygons" being the first of many I've already encountered.. plays on site fine, but in your software, broken.. 'An error occurred. Please try again later.' This means you randomly have 'embedded playback' blocked on a bunch of your own support videos that you guide new users to. 🤦
The problem with via delay is that it is not so simple to calculate, there is no closed form solution and it depends on several factors to get correct. There is a model from Howard Johnson's textbook that many calculators will incorporate, but that model is grossly incorrect and Howard Johnson even says in his textbook that his model is incorrect, so if you ever see someone provide a via delay calculator it is most likely wrong. I am surprised at the number of people that point to this model from Johnson's textbook, and yet they fail to look forward 2 pages in the textbook to see where Johnson explains how and why it is incorrect. I've done videos on this topic and have pointed out many times how these calculators which purport to give this information are incorrect.