APB Protocol Basics | APB Protocol Explained | APB Interface | APB Bus Protocol | AMBA APB Topology

Hello Guys,
In this Video, I have explained about What is APB Protocol, How the APB interface or the Peripheral components will look like from a system perspective and along with APB signal descriptions.
Keywords:
Advanced Peripheral Bus, APB protocol basics, APB interface basics, APB explained, Basics of APB, APB Write Transfer, APB Read Transfer, APB Write Cycle, APB Read Cycle, AMBA Bus Architecture, AMBA Family Protocol, APB Protocol Concepts Overview, APB Overview, APB Tutorial, NPTEL, nptelhrd, AMBA, APB Master, APB Slave, APB Bridge, APB Address Decoding, APB Bus architecture, APB Topology, VLSI, VLSI Design, VLSI Interview Questions, VLSI Design, APB Interview Questions, APB Transfer Slave Error, APB Write transfer with Wait Cycle, APB Read transfer with Wait Cycle, APB Write transfer without Wait Cycle, APB Read transfer without Wait Cycle, APB Setup Phase, APB Access Phase,
Chapters :
00:00 - Introduction
00:34 - What is APB Interface?
01:49 - APB Bus Topology
09:06 - APB Signal Description
17:18 - APB Protocol Waveform
18:36 - APB Setup Phase
19:05 - APB Access Phase
#APBProtocol #VLSI #APB
Credits:
1. A Magical Journey Through Space by Leonell Cassio | / leonellcassio
Music promoted by www.free-stock-music.com
Creative Commons Attribution-ShareAlike 3.0 Unported
creativecommons.org/licenses/...

[@Electronicspedia]

Please Like, Share and Subscribe to my channel ua-cam.com/channels/3mTACG8vPWsHQFMfxzeDZg.html

[@user-wi1ke7ws5s]

You are very good honestly, in all my years in university i never had a teacher that explains better than you.

[@venkateshprathipati3907]

Thank you so much.

[@keepcalm8420]

Your whole series on APB is really good and probably one of the best made on youtube. Really appreciate your effort. Thank you for the clear explanation. Hope you can make more videos on protocols such as AHB, AXI etc.

[@Electronicspedia]

Hi, thank you so much that you liked my videos, I will definitely come up with more videos on protocols like AHB, AXI and PCIe as well, keep watching Happy learning !!!

[@reubengeorgemathai7329]

Great video!

[@noufalnishath1937]

very good explanation

[@yogishmurthy9320]

You're explaining in a awesome way sir.
Keeping continuing sir

[@Electronicspedia]

Thank you 😊

[@user-oo8vi5cf1x]

Thank you ❤

[@navyamalla7362]

nice explanation

[@kartiknit1]

Very nicely done video! thank you for this. Do you have a video on AXI? If not, please do share it :)

[@sailajapeddakotla8248]

Hope you can make more videos on Protocols

[@tarekamrani7155]

Best Teacher Thank you very mutch

[@Electronicspedia]

Thank you 😊

[@Muskaanhayat]

Thanks sir

[@shanyuth836]

Very good explanation. could you please explain about axi?

[@maksymkloka7819]

Keep making videos.

[@rambabukasetty8975]

Nice explanation. Can you upload video on AHB.

[@gokulp6878]

Amazing .can you please explain ahb protocol

[@Electronicspedia]

Sure will plan for it. 👍

[@venkataravindrabiyyala1759]

sir please do videos for AHB and AXI protocols

[@Electronicspedia]

Sure.

[@sankasuvarna1900]

very nice tutorial sir do u take any online training sessions if yes pls share details i will join

[@Electronicspedia]

Hi, No I just make videos here for everyone's benefit. No other online classes.

[@oviya.n1317]

@10:18 u are saying APB is a single bit transaction. As per the protocol the bus width can be upto 32bit wide. Can u clarify this. ALso at the beginning of the video u are calling APB as single channel. It has got channel for read ,write right?

[@Electronicspedia]

Hi,
It's not single bit, I had said single beat.
Here beat refers to one single transaction in a burst.

[@sailajanarayanam7707]

Sir can you explain ahblite topology

[@Electronicspedia]

Sure.

[@anilkumarkurra1314]

Hai sir, shall we logic data type in verilog.
For both input and output?.

[@Electronicspedia]

Yes,
Input logic siga,
Output logic sigb
Both are valid.

[@anilkumarkurra1314]

Okk sir tanq

[@ARUNKUMAR-oy1gk]

@@Electronicspedia but...sir...logic keyword is only for sv right....not in verilog

[@Electronicspedia]

@@ARUNKUMAR-oy1gk yes you are right. Thanks for pointing out.
Actually I have been using system verilog for quite sometime and I often forget what is there verilog and system verilog.

[@ffushiguro]

In verilog
for design
input - wire
Output - reg
For testbench
Input- reg
Output - wire

[@neelimareddy4139]

How many slaves are there for an apb

[@abhishektalukdar8471]

Too much advertisement.