#12-1 Use of always@(*) in verilog || combinatioal logic design in verilog || very important concept

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  • Опубліковано 12 січ 2025

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  • @fact4education
    @fact4education 4 місяці тому +1

    you deserve million views... Thanks Keep it up

  • @Billiboo-j3z
    @Billiboo-j3z 5 місяців тому +1

    You are gem ❤

  • @sgovindraj4619
    @sgovindraj4619 2 роки тому +1

    your explanation is very super sir ....thanks you sir ....

  • @kobafn4598
    @kobafn4598 8 місяців тому +1

    The other video you said that the always @() ran continuously and now you say it never gets executed.. which one is it? Or did you mean always (without '@' and '()') runs continuously?

    • @ComponentByte
      @ComponentByte  8 місяців тому

      Please tell me the tutorial where I have said it runs continuously, I will go and check it and if requires I will rectify it.
      It never gets executed is correct.

    • @kobafn4598
      @kobafn4598 8 місяців тому

      @@ComponentByte but does the always block without anything else run continuously?
      This was in this video (maybe I heard wrongfully):ua-cam.com/video/-PCHSFyszoc/v-deo.htmlsi=q7lsRlaOxBUNbVHL
      At 12.00 it's written and you said it outloud

    • @ComponentByte
      @ComponentByte  8 місяців тому

      Yes, always( without @ and () ) runs continuously

    • @kobafn4598
      @kobafn4598 8 місяців тому

      @@ComponentByte thanks! Other question: can you use gate primitives only in structural modeling or can you also use them in behavioral modeling, and can you only use cases and statements in behavioral modeling comparing to structural where you can't?

    • @ComponentByte
      @ComponentByte  8 місяців тому

      @kobafn4598 I have uploaded tutorial on structural and behavioral modelling. Please watch it and your many more query will get solved.

  • @Aks50c
    @Aks50c 2 роки тому

    Please also share the ppt it will be highly helpful for us while revision.

    • @ComponentByte
      @ComponentByte  2 роки тому

      I have told the reason for not to share the PPT. Sorry, I am forced to do so. Any other type of help will always be provided by me.

  • @RahulAgrahari900
    @RahulAgrahari900 2 роки тому +1

    sir plss make full course of verilog .u are really very talented and explaining the concepts in very easy way ,,

    • @ComponentByte
      @ComponentByte  2 роки тому +1

      I have uploaded all the concepts of verilog and this is enough for any fresher looking for a job as a RTL designer but he or she must be good at digital design concept also. Thank you. If I feel some concepts have been missed then I will definitely upload it. Thank you.