UVM Testbench Architecture

Поділитися
Вставка
  • Опубліковано 30 січ 2025

КОМЕНТАРІ • 5

  • @PranathiBethi-ij7kx
    @PranathiBethi-ij7kx 9 місяців тому +1

    Great explanation! Thanks for your sessions.

  • @AnkitRaj-qv2wq
    @AnkitRaj-qv2wq 3 місяці тому

    More videos?
    Is all the videos present in app?

  • @Rahulkumar-nc9nm
    @Rahulkumar-nc9nm 9 місяців тому

    Really great work, can’t wait to listen upcoming classes

  • @TheLegend-uw4pw
    @TheLegend-uw4pw 5 місяців тому

    Mam, please explain TLM ports in UVM. Not able to find proper source from which I can understand the concept.

  • @mayuripandey4402
    @mayuripandey4402 9 місяців тому

    Thankyou mam.. your teaching style is something i can grasp easily. All thanks to your effort.
    I have a doubt,
    Is it possible to have seperate interface specific to driver and another interface specific to monitor along with the main interface specific to protocol ? I saw one example and couldnt understand the need of having that kind of architecture.
    Also, the top module you mentioned is extended from class ?