Відео

11. 5bins

if the FSM steps into one of the unwanted states, make a transition into the reset or even better a known state to signal this problem. however, maybe..., better solution to code the states in gray - if it possible at all, - to avoid unwanted state. In this case, only valid states can occur.

Please make full course on UVM

More videos? Is all the videos present in app?

Hello mam , I am recently graduated, I have skills Like UVM,SYSTEMVERILOG, PYTHON, CPP,COVERAGE VERIFICATION, DIGITAL ELECTRONICS and have two projects and some certifications from NPTEL.How should I do my resume.

mam, really it is a great initiative by you to guide students in very detail through these videos.Definitely these will help all students.You have covered every nook and concept and have given these questions. One who completes all the 111 days will definitely gains confidence. Thank you very much mam.

Where to learn system verilog and uvm , Little bit knowing verilog

Hello mam actually i am pursuing m tech in svnit this playlist helpful?

Hi, what to focus in python scripting for interview foe verification job? Please make videos for that too. Thanks

Mam if we specify logic[2:0] will it work? logic[2:0] why is not equal to with logic [3]?

Ma'am please upload more advanced topics of system Verilog such as environment, modport, interface, generator, virtual interface, semaphore etc.

Thankyou so much ma'am

Wunsch Tunnel

Everyone uses fruit to explain associative arrays, even though no one EVER uses associative arrays to sort fruits.

Mam, I have a doubt regarding 5th question mam. SR latches are asynchronous by default and when we add enable (gate), they become synchronous. SR flipflop have clock pulse which makes them synchronous by default. How do Gated SR flipflops become to be called asynchronous latches, mam? I am not able find any online resources for this question, mam. Please tell me where am I wrong and clear my confusion, mam.

Very Informative Videos😊

Mam, can we post our answers as a pdf on linkedin and also tag you in the post? Also, Can we take a screenshot of these questions from the video and add it in the pdf, Mam?

Hi mam. I couldn’t find the reference to this video provided- system Verilog essential series with a title program block.

Thank you mam

I agree #switispeaks

Can you please recommend uvm text book or material

1. transmit(p), Here p is not defined, instead, we have to give b. 2. Randomizes the value between 1 to 65535, such that a value is very smaller compared with b and c, b will be greater than a and smaller than c , c will be greater than a and b values 3.@0: start fork...join example @10: sequential after #10 @10: parallel start @20: parallel after #10 @40: sequential after #20 @50: sequential after #10 @60: parallel after #50 @60: after join @140: final after #80

Maam what does priority decoder mean? Unable to find any resources for that, online it shows that it is the same as priority encoder.

Hi Mam, shouldn't gated SR latch be synchronous, in the question it says asynchronous?

Elyse Unions

Day 1

I agree #switispeaks #111daysofverificationchallenge

Thankyou mam..

Hello mam, As you are working on FORMAL VERIFICATION, Can you start a playlist related to FV topics? or Topics to learn and How to prepare to be FV Engineer.

by default (if we not mention any timing delays) the input skew will be 0 and the output skew is 1

Wow nice content on system verilog ❣️

Thankyou mam

Very informative Sweety. 👍🏼👏🏼👏🏼👏🏼

Thankyou mam

Thankyou mam.

Thankyou mam. Waiting for other lectures series as well. 😊

Mam, please explain TLM ports in UVM. Not able to find proper source from which I can understand the concept.

Nice Content. Got to learn New thing.

I haven't learned Digital Electronics, VLSI now can i refer to this playlist for my placements is this sufficient? or i want to learn in depth? @SwitiSpeaksOfficial

Hi mam. Please provide with example if possible.

Mam, please give one sv example for this video Extremely for srandom, get_randstate, set_randstate

I agree #switispeaks #111daysofverificationchallenge

I only see explinations. R u not practically showing ? Any reason ?

can you please tell factors that affect testability of design ..apart from controllability and observability?.... And also please suggest good source for DFT

mam plz put eda links

Where we can find the answers mam?

Hi,I was trying to find out the solution for the 4 th question,but unable to find it ..could any one please post the solution for it ?

Ma'am I'm a trained fresher can i add this training as a professional experience?

Can u share some fresher resumees

Hi mam