Repetition Operators w.r.p.t SVA (System Verilog Assertions) SVA VIDEO #07
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- Опубліковано 15 січ 2025
- This video is all about the introduction to Repetition Operators (Consecutive & Non-Consecutive) with respect to SVA (System Verilog Assertions).
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Thank you for SVA series 🤩really helpful
=> ##1 a ##1 is confusing. it feels like a may not be high after the clock cycle when we see the blue box, but a cycle later. shouldnt it say -> instead of =>?
Thank you very much for a wonderful series 🙏
Thanks, upload more videos... thanks for good content...
these are very usefull,can you please provide next series of videos?
what happened to the go to operator video? lol
very helpful. Please plan for next videos
Sure 👍
Sir, can you please explain of how to execute these waveforms with all those flags
why there is ##1 before a[=2], though you have used the non-overlapping operator
Please complete the series upto SVA Control tasks... plss sir it will be very much helpful for us...
Will upload new concepts soon..
Please upload further videos
Sure.. :)
Where are the next videos?
Thanks for the information, its good. Please cover remaining topics
Sure.. :)
can u plz expline the diffrence between non consicutive and go to
sir ,thanks this information videos and try to do remaining topics please
Sure .. :)
Sir, please next videos of SVA?
If possible will upload in the next week.
Thanks :)
Non continious will never fail ?. as a can get high any time after many clock cycles non continiously
you have used non overlapping operator but mentioned ##1 delay
Happy Birthday Bhai..
Thank you Gupta Sir..❤️😄