IBM Power10 A Glimpse Into the Future of Servers
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- Опубліковано 30 січ 2025
- Check out the main site article: www.servetheho...
In this article, we discuss the IBM Power10 architecture and some of the new and unique features of IBM's Q4 2021 Power platform. Not only do we discuss some of the cool features of the IBM platform, but we also discuss what they mean for the future of Intel Xeon (Sapphire Rapids), AMD EPYC (Genoa), and future Arm processors such as Ampere's next-gen and Marvell ThunderX4.
We are going to update the main site article during Hot Chips 32 (2020) with additional microarchitectural details. Instead of going through them in this article, we wanted to focus on what the IBM Power10 can tell us about the future of servers and the pain points IBM is hearing its customers ask the company to address.
I have worked on power systems since the power5 generation. They are amazing machines.
Amazing stuff here. In the 90's I used to be subscribed to the IBM Systems Journal and saw things that were 10 years into the future.
Man, thank goodness for you, I don't think alot of companies will be able to get this info across.
I'm watching this video almost a year since you've uploaded it, so you're right, maybe a year after I watched this.
The importance of the architectural innovations cannot be over stated. However, it is a long time coming. I thought we'd see these types of memory architectures with Memristor/3D XPoint
In theory, you could make an OMI controller for those new memory types. My sense is that is the near-term path to higher memory capacity.
Installing a Power 10 tomorrow.
Sweet! I wish I could do the same.
First of all you need to respect that IBM subbornly maintains its POWER architecture while almost all good RISC architectures are long gone and forgotten. And quite frankly, I admire IBM for that.
However, all these new technologies are designed to solve problems, IBMs customer base has - while >90% of the overall userbase does not.
All "new" IBM technologies, like PowerAXON (remote memory access), OMI (the "new" memory bus) and CAPI are not so new. Let's take them one by one:
CAPI: Having a (cache-coherent) interface to coprocessors is a Good Thing(TM). It's actually such a good idea, that it has been implemented multiple times. Call it Hypertransport (AMD), Omnipath(Intel) or CAPI(IBM/Power consortium), they are essentially all suited for coherent coprocessor attachments. The reason, that all fell back to CPU-to-CPU interconnects being soley used by their inventors was, that there is no standard. Companies like Nvidia will not build a Hypertransport, an Omnipath AND a CAPI version of their chip. Its not scalable in economic terms. There have been multiple attempts to create a standard, all failed.
Well, not *really* all. PCI-e has extensions for exactly this usecase. And nowadays on all modern CPUs, PCI-e controllers are actually integrated in the CPU and are able to directly r/w-access the CPUs cache(s). That works so well today, that AMD is actually using PCI-e as a CPU interconnect on EPYC, both package-internal (between CCX) and package-to-package in a two-socket config. So, instead of developing their own interconnect standard, AMD is actually using PCI-e exactly the way, it was intended to be used from day one, when it still was called 3GIO or HSI. Nowadays, there is no need for CAPI anymore.
OMI: It is clear, that parallel differential signalling is coming to an end. With DDR, you simply need an enormous amount of CPU pins if you want to have enough parallel channels. EPYC already has >4000 pins which include 8 DDR4 channels. Having more than 8 memory channels using DDR is next to impossible. Routing all the signals for your memory bus across you PCB for 8 channels at 1,6Ghz (DDR4-3200) is already a nightmare. It is next to impossible for 12 or even 16 channels. If you switch to serial interfaces with ultra-high speeds, you need a controller on both ends - the CPU and the memory module. This not only increases cost for memory modules, adds complexity and lets your power-envelope rise through the roof, it also adds latency. A lot of latency. This is why it hasn't already been done (although RAMBUS actually tried something alike back in the days). To be able to accept such a large latency penalty. you have to add insanely big caches to the CPU. Which is what we will see in the next 4 years, when CPU makes will add HBM-like memory stacks on their CPU dies. Then the world is ready for OMI. However, this will need to be a cheap or free standard, as all memory makes will have to support it. Remember, why RAMBUS failed? Go look it up. "Cheap or free" are two words not going along quite well with "IBM".
PowerAXON: Having a uniformly adressable memory across a cluster of independant system is a good idea. It is actually so good, that it is already there. Sort of. Actually the interconnect is there, but contemporary CPUs do not support the addressing model. The interconnect is Infiniband. It was exactly designed to be used for that (reference: Infiniband fabric). It's just a fact, that nobody uses it. RDMA is actually a special case, as it describes the remote-memory access by a device, which is not a CPU. Add RDMA capability to your CPU and viola - remote memory access. The problem again is latency. You stated a "50-100ns penalty, which would be quite good. Infiniband EDR is at 500ns, but this includes two transceivers, which - to my knowledge - is not the case with PowerAXON. Infiniband stil struggles with adoption as Intel stubbornly refuses to support it. To cope with the latency penalty, applications would need to be re-written to account for the latency penalty while accessing remote-memory. That would require some sort of memory-hierachy. However, applications have never and most likely will never be re-written that way. Instead, applications are re-written to scale horizontally by distributing chunks of workload to distinct systems. I doubt, PowerAXON will be successful in the non-IBM world, while so many before have failed.
All of the above technologies however, are suitable to solve IBMs problems. Mainly in their mainframe business. IBM has total control there: OS, Software, Systems- and memory architecture, peripherals and the like. All technologies enable IBM to build insanely big and powerful mainframes - and earn a fortune by upgrading their mainframe customer base. Which is very large.
RISC is dead? Isn't ARM based around a form of RISC?
@@Speak_Out_and_Remove_All_Doubt Which is why I wrote "ALMOST" all good RISC architectures....
AMD uses PCI-E? I thought it developed it's own Infinity Fabric?
@@virtualinfinity6280 I'm not looking to argue but isn't that like saying almost everyone has given up on x86 because there's only really Intel and AMD left?
@@Speak_Out_and_Remove_All_Doubt That is why I wrote "RISC ARCHITECTURES" and not "RISC companies". Almost all RISC architectures are dead. x86 is not. It is actually predominant. Regardless of the number of companies producing x86 chips.
Patrick is so engaging and enthusiastic and I always learn something new. Thanks
Obviously x86 is pretty different but how different is PowerPC vs RISC-V vs ARM in terms of architecture?
They are both load store risc ISAs that are open. The nitty gritty details you'd have to read the entire ISA. RISC-V is not exactly complete yet in all aspects (SIMD for example). POWER is pretty mature and has existed for decades.
And it’s now an open design like RISC-v, which is pretty cool, prob v attractive at hyperscale
ARM is also pretty old. It came out originally in 1992.
I've watched quite a few of your videos and I enjoyed this one the most.
The company I work for (printing industry) has been using the Power series for what seems like decades now - upgrading to the Power10 soon
Awesome content and super to the point delivery ;) well done!
It is not the differential signals of DDR that take die area. OMI uses mostly differential signals, hence they are called DDIMM. DDR only uses differential signals for clock and data strobe. The issue is the massively parallel multi-drop bus, timing training and protocol logic of talking directly with the DRAM. It will be interesting to see if OMI takes off more than FB-DIMM did.
Also, how big are the local parallel caches going to have to be? Arent we going to end up back where we are now?
Such a good presentation (also quality video)!
OMI is exciting and we need this! this could mean that moving to fiber interconnects will be made even more so easier. POWER10 sounds like a game changer!
Power is used in the PowerSystems (pSeries and iSeries) and in their zSeries mainframes. Though in the mainframe space, you're not officially running Power code at the OS level. IBM loads microcode on to the Power CPU that makes it present itself as a mainframe CPU and is backwards compatible with the instruction set back to the 1960s S/360 mainframes. (Like on chip emulation)
POWER is not used in zArchitecture (it was like 15 years ago that they were called iSeries, pSeries and zSeries..). zArch is using its own CISC based processors, that share some functional units with POWER (like its decimal floating point unit, and previously GX bus) but not much else. Z15 is the latest.
@@henrikwannheden7114nope Z16 is
Solid video on IBMPower10.
I commented 2 years ago just below and actually changed my mind. I want this Power shyt and IBM gone already. Have you seen any young person ever review this thing? It might be around for some time but not very long. None of IBM's UA-cam marketing videos allow comments. I'm not surprised. I remember when there were printed IT magazines IBM had those adds that never talked about their products. Those adds basically said if you have IT problems contact IBM. They will sell you way overpriced solution. As always cool video Patrick.
first time i heard the term "they're just slide-ware". cool!
Whoa. Didn't know any of that was a thing. It's awesome.
I'm so excited for Power10. Power9 aio is great for flexing their capabilities, but 10 will show the direction the entirety of the server world will move in. I've been hesitant to invest in a Raptor system so far but I'll 100% grab a power10 system if they release one
I totally agree. This is super exciting
For general computing Power is already good enough. IBM completed successfully mind-boggling task of porting whole software stack from OS, compilers to heaviest software in big data to Power, and basically it's ready out of the box. We have now proper choice - Intel x86, AMD x86 or IBM Power (ARM is NOT ready yet) for actual deployment right in DC like now.
Talon/Raptor hardware is basically devbox, IBM provides virtual Power servers, and sometimes Power9 pops up on AWS bare metal, but pricing is rather high. :(
@@Vatharian ARM datacenter processors like Ampere Altra Max and AWS Graviton 2 based on Neoverse N1 and future processors based on Neoverse N2 and V1 like the Marvell Octeon 10 processors and Sipearl Rhea are ready for servers and data centers. Nvidia Grace CPU is also an interesting CPU for heavy tasks like machine learning and high performance computing.
Apple already has ML and Neural Engine *cores* on their silicon in Phones and Tablets - and there is no doubt they will expand their use in their upcoming Apple Silicon desktop SoC chips. It's going to be fun to see where this all leads!
That was AWESOME! Thanks!
Hello STH, could you clarify if the max memory configuration of 2 petabytes (3-6 terabyte per dimm) is with a Volatile type of memory or a Non-Volatile kind?
IBM used future memory types. ODI has options beyond DDR4/5 possible.
Pretty soon 640PB ought to be enough for anybody... :P.
AMD was rumored to go SMT4/8 after Genoa from Zen
Thank you for this. Good info.
So why did IBM lose the super computer contracts to AMD then? Maybe it wasn't bringing something exciting enough to the table what they needed? Is there any analysis on this topic?
We did not go into this here. That is a big topic itself. Also PowerAXON does not speak NVLINK in this generation which was a factor in the HPC wins
@@ServeTheHomeVideo Thanks, maybe it is an idea for a future video or in-depth article. ;)
Great presenation! I like it! I wish IBM implemented STM2 also, that is allow 2 threads per core like current x86 processors. Not all code can take advantage of 4 and 6 threads per core. It can be wastement in some application.
By the way, ARM architecture takes the opposite approach. It thinks that SMT is bullshit and that's why almost no ARM architecture, neither standard ARM architecture nor custom architectures support SMT.
Man, I wish Nvidia just gifts me a DGX-A100 someday.
Can we get one too?
@@ServeTheHomeVideo If you do get one, I will help you benchmark it with Deep Learning applications for sure if you want it. :) Great video!
Or just wait a decade or so. What took an entire rack cabinet from 20 years ago (I remember being blown away seeing a bunch of Sun Big Iron ~2004), is now pretty mediocre. Wikipedia is full of dead links of Sun before they got taken over by the dark side. I'd love to benchmark my desktop against a fully loaded Sun E10K, I have a feeling my desktop would win.🤔
@@garethevans9789 Two weeks ago I scrapped 'Cisco academy' at work. Five racks, absolutely chock-full of top of the line Cisco offerings collected from different departments after decomissiong, like stacked 100G switches, hubs... oh wait, did I write 100G? Out of habit, I suppose... so 100Mbps switches, hubs, firewalls, routers, couple 1G devices (think over 2U module in 8U chassis that has... 6 ports), servers, and gods knows what else. We asked several schools in the area if they wanted it for training (everything was functional), but none accepted, so we had to scrap (no private gifts policy). My point is, single 48+4 1/10G switch has more bandwidth than that whole museum.
When I was in college in early 2000s my department got new supercomputer, 50 TFlops monster, and I have currently more sitting under my desk in two render boxes, casually sipping a little over 2 kW under load. On top of that I have bigger SSD than this supercomputer had total capacity in its SAN - so you're probably right...
@@Vatharian 2KW makes a good heater. It will be cold tonight. 7 degree C. Will be nice to have those running
i love ibm
This would prob be a beast in a home pc.
Hard to power though
@@ServeTheHomeVideo it uses alot of power?
i just want IBM power on the desktop as an actual competitor to x86
Well without windows support no one will buy it, there are workstation boards with POWER9 out there. The company is called Raptor, but they are kinda pricy between $3000 and $5000.
@@JohnSmith-yz7uh i just wish there was a more consumer friendly version of the chips. like to compete with ryzen or the core series. I do understand what you are saying thoughj
@@josephroblesjr.8944 ARM will eventually take over the laptop and desktop PC market as well as the workstation and server market.
4:35 i think you meant to say "parallel", not "differential"
Wow, it's basically a gymnasium-sized barbecue.
now I understand why IBM P series memory are that expensive,they have build in controller on borad
Game Changing !
even some HP SuperDome FLEX does like so many nodes as one "system" upto 32 processors and 48TB ram
1:17 hard choice
Ha! There was a funnier version of that one that got pulled last minute.
Sounds exciting, not sure how well this will compare against Genoa end of 2021. 🤔
Talked Genoa a bit since they will be contemporaries along with Sapphire Rapids
@ServeTheHomeVideo
Yes, you did.
Will be an interesting year for the server space.
IBM POWER10 will outperform AMD Epyc Genoa and Intel Xeon Sapphire Rapids.
With disaggregated memory and dark fiber between your computer and a nearby datacenter, the old meme of "downloading more RAM" may soon turn out to be true!
It will not happen. Even in a Asian highly populated city where I live, the average distance between the data centre and residential area is still more than 10 miles away. Not a single citizen can have his/her private optic cable direct to the data centre. The government will not grant you the permit to dig up the road to lay your cable unless you are a telecomm provider or a mobile phone network company etc.
@@catchnkill I jest. There are a lot of nanoseconds in even one mile ua-cam.com/video/9eyFDBPk4Yw/v-deo.html
Omi, is a great tech. However, hope it doesn't introduces too much latency.
OMI is high bandwidth low latency memory bus.
Isnt that the architecture has its beginnings back when IBM was designing that Cell processor for Sony Playstation 3? I have no idea just guessing that this could be the further evolution of that cell architecture technology..
Way before the Cell processor, I was working on RS/6000 Power hardware in 1990, basically POWER1
@@freddown Yes the POWER ISA arctually began with POWER1 in 1990. It has since evolved into the PowerPC architecture beginning in 1993 and by 1998, the original POWER ISA was deprecated. In 2006, the PowerPC ISA evolved into the third Power ISA.
50-100ns hit going to another box is *nothing*. A load from local DDR is going to get close to that 100ns number anyway
Awesome
Wow if you were to strategically locate this infrastructure in datacenters around the globe, you could leverage for prime time applications during the day in any given region and use And to migrate virtual instances of heavy compute to infrastructure that is under utilized, get Maguire ROI. You could even lease time to third parties and IT could go from a cost center to profit center in large enterprises.
You missed out the impact the technology would have on cloud gaming.
If power 10 ended up being a Stadia CPU powering a game like Call of duty: Warzone the total memory used across all 120 players would be a fraction of what is used by 120 PC or console players.
So, 16 * 30 * 4. Wow, that's 1,920 threads in one chassis!
IBM
Who wouldn’t watch the whole video????
these processors are some chunky monolithic boys
They now have dual die so not just monolithic!
@@ServeTheHomeVideo Dual chip and multi chip modules are nothing new for IBM POWER processors. All POWER CPUs have been available in multi chip module configurations.
If I understand this correctly -- PowerAXON = RDMA at the OEM level.
...and then IBM released pricing for Power-10.
Why dont they go really mad and put stacks of HBM 3 next to the die. Maybe they can get 64GB of L3 cache.
Manufacturing. HBM 3 are 3D chips using TSVs to connect the dies vertically. Very difficult to make and very expensive. Thus very niche market. TSMC is now so happy to produce those Apple chips and just will not care to make such difficult stuff
2:12 ~ good mention, #cool, which of you are not running. somehow it seems impossible to turn off either of the 4 corner chips. So something like Knights Templar Crusader 4x4 grid from the middle outwards. ~ The Symmetric Multiple Thread(ing) never made sense to me, except math matrix of 128 SIMD=64+64=32+32+32+32=16*8, yet 512bit and 2048 exist out there, the threads thing also never made sense, because "out of order" operation, execution, delay prefetch, services, always meant since Windows NT=Jesus, New Technology, allowed services to do swing dancing, so maybe 1,000 threads per core = explains how intel 8088 1 million instructions persecond, while running 5 or 10 megahertz max (needs checking, completes 1 operation per 5 or 10 clock cycles, huge difference). and 233 mhz and 1.8Ghz and 2.0 GHz (Weirdest 200 Mhz performance snappy responsive boost ever, memory L1, L2, internal clock or DRAM clock magic, was DDR400\800 so 5x was a pleasant wow. compared to 1.8GHz, always told the multiplier of timing did not matter, insultingly wrong) and then 4 Ghz and 5(000) Ghz on tv, youtube, onscreen typing speed looks about the same to me. Using google search auto complete is faster than, google docs and microsoft word. Use my document library, and help me the fuck out!
6:45 ~ Damn. When you opensource your API or ISA and logic gate maps, i sort of think Google Authored their new Einstein System. I was saying we need to address the maximum of SDUC sandisk cards, 128TB, are they multiplying this per 16 channels, 1 per 16 cores.
8:42 each processor for speed reasons, would have its own address table. some sort of logic, master file table, controls cores = nodes, access and just a bunch of drives, or locked to another drive sector management dip switch add or subtract who can write. for speed i would ignore who can read, i like reading, and cores can individually encrypt their storage to secure any node, admin, client reads.
11:43 ~ #Hotchips really is the most exciting, should we be #masturbating while they are presenting what seems to be industry secrets, that i have never been republished or revisited in detail outside of this dimly lighted, possible pole dancing disco ball slide show. if any one at home is trying, i respect that, it is so intimate with details we never hear discussed, that it definitely seems a marriage pollinating exposition.
Still no vector processor design additions.....kinda lame
There are lot of vector and matrix processing SIMD extensions added to POWER10.
Thks, en.wikipedia.org/wiki/POWER10
With the SMT8, you make it sound like there is some benefit to 30 "cores" with SMT4, yet you don't explain why it would be a benefit... You also make it sound like the Power10 will only be available in the 15 core config. So the 30 core version would be something like SMT2, and then running SMT4 on that SMT2 setup.
What constitutes a core is what functional unit share L1/L2 caches, scheduler and registers. So a SMT4 core share all that with its SMT4 twin, and one SMT2 cores share its caches, scheduler and registers with three other SMT2 cores. In a regular SMT2 x86 system, each SMT2 core has those facilities for themselves
The hypervisor (PowerVM and KVM) seems to have logical partition facilities that are able to securely partition a core down to a SMT2 slice. Some workloads really benefits on being spread over as many threads as possible, while others need the extra cache per thread that comes with a core not handling that many threads. This seems to be able to be dynamically adjustable by the hypervisor. So.. It depends.. Somethimes 2x SMT4 is better than 1x SMT8, sometimes it's not.
IBM POWER10 will have upto 30 SMT8 cores per socket.
2030, Notepad will require 64GB RAM.
amazing!, now please give me a good intel server with GPU and no worries about finding the right .DEB file or python libraries!
#IBM still around?
The share price ain't doing so well. Still lagging after coronavirus, unlike pretty much every other tech stock. Says a lot, I think. Annoying cos I bought some!
Captive user base = locked in. Future will be AMD and Intel, I'd be surprised if ARM made any inroads in the data center. IBM is only really used for AS/400. Intel and AMD chips have plenty of cores/power right now for virtualisation. IBM is very niche in the data center. Nobody wants PB of memory in any machine, but having a couple of TB is nice, and .. practical. Putting too many VMs on a single box isn't such as good ideals. Intel and AMD put the memory controller on the cpu die for good reason, it would be interesting to see if in the future technology advances meant it made sense to decouple. IBM kit is .. very expensive. AWS and Azure would continue with their commodity hardware approach. Having said that, love to see what they can come up with. Unfortunately IBM tends to invent betamax-style products, whilst the world buys VHS.
@@owowowdhxbxgakwlcybwxsimcwx very interesting, but unlikely to have appeal to those who spec and choose hardware in most corporate / enterprise environments. ARM is unproven for Windows, and not supported, as far as I know, for VMware. Most physical kit runs virtualisation like VMware or Hyper-v. Intel / AMD are proven parts.
@@owowowdhxbxgakwlcybwxsimcwx had a further look at this, server cores, cache, memory capability, PCIe lanes etc look really good, very impressive, but it does come down to support. It would have to run VMware, other hypervisors, Redhat, CentOS, Windows server, etc, to break into the DC market.
@@JonathanSwiftUK IBM POWER CPUs run various Linux distributions like RedHat, Suse Enterprise Linux, CentOS, Debian etc. along with IBM i and AIX and virtualisation software like VMware. Plus Google Cloud is already using IBM POWER CPUs.
@@atisbasak Yes, it's true IBM has a presence in the data center, particularly with AS/400, but on price I don't believe they're competitive with HPE/Dell. Like Apple they are a closed eco-system in terms of their PowerPC offerings - vendor-locked. Where they use Intel CPUs (and they do, I've swapped Intel CPUs in IBMs) they should be viable for those who are IBM fans. Cisco (I'm thinking UCS) use Intel chips and have a good Enterprise management platform. I don't have enough experience of what management tools IBM have. HPE/Dell have good management tools. Managing hundreds or thousands of servers needs good management tools for deployment / maintenance (firmware/software/driver upgrades). 20 years ago Microsoft told me to buy AMD for Exchange servers and Intel for everything else. These days just about everything is virtualised, so when managing hardware and hypervisors integration is needed. Then you have storage, and that ties in with your integration, i.e. deploy these hypervisors, on these hardware platforms, and use these LUNs.
And in addition to that, ARM servers CPUs like Ampere Altra Max and Marvell ThunderX3 based on Neoverse N1, Octeon 10 based on Neoverse N2, Sipearl Rhea based on Neoverse V1 and Nvidia Grace CPU based on ARM will revolutionise the data centers in all workloads including machine learning and high performance computing.
Those new jump cuts really aren't doing you any favours
Still gaining confidence the S1 will keep focus when I am looking at the C200. This is partially testing out that feature.
Can we finally get away from all this x86 and x86-64 nonsense please and leave the mess of CISC in the 80s where it belongs.
That memory controller tho :). I want a POWER10 with a bank of HBM2 for ram :D
with HBM2E you can basically max out that 1TB/s interface with just two stacks.
@@tommihommi1 So create a special SFF mobo for workstation use with built in HBM2e
Finally a promise from IBM for my new media server. I'll keep it down to 1PB of RAM. It should be OK. If something happens I can always invite a 64 year old expert to fix it. Amazing this crap is still around ...
15c/120t CPU? What the actual f**k?
Sorry for swearing but honestly, why so many threads for so little actual cores?
A Power10 thread is a bit different than a Xeon/ EPYC thread
@@ServeTheHomeVideo I'm currently designing a NAS server for a raspberry Pi in Node (which is a JavaScript runtime)... 4 ARM cores is plenty of power to simply serve a few files and do automatic backups through my app, even more since I'm splitting most tasks to multiple threads, but I'm still kind of interested who exactly would need a CPU like this, it's actually more like a GPU from the thread prespective (Don't get me wrong, I'm looking kind of loosely from that perspective, but still)
I guess that's more about the flexibility, you could have a few *strong* cores or more weaker cores, if that's possible to split them like this... Also this approach could mean you could design your software in a way that would utilize cores normally for heavier tasks, and use the smaller "splitted" ones to do some 2th grade smaller tasks, meaning a more optimized CPU load.
Guys, I know the Power architecture in and out. This is a whole load of BS. The main reason other companies don't care about SMT and memory clustering is because the world has moved on to scale-out and cheaper models with the best virtualizers like VMware. Power has a bullshit virtualization engine, PowerVM, and noone wants to use it.
This is the whole commodity vs bespoke computing argument, which I too thought was decided 20 years ago for 99.9% of folks. I'm guessing IBM think as long as they offer something slightly cheaper as an upgrade then there customers throwing it all in the bin and going with someone who offers a migration onto a standard platform..... they'll win.
Fat protogens
бла бла бла.... много рожи мужика и мало картинок!
No, a lot of us don't use Power CPUs, but nice try to justify the contents IBM sent you. :)