Thanks a lot Nikita that you love the content. We will try to do our best, keep supporting. You can also visit our blog ( www.teamvlsi.com ) and follow the blog.
Hi Adil, I have added the same in this article: www.teamvlsi.com/2020/08/end-cap-cell-in-vlsi-boundary-cell-in.html You can refer the HOW TO PLACE SECTION Thanks
Hello Sir, Maximum distance between two tap cells is fixed and follow technology DRC. But when placing tap cells in vertical column and if macro comes in between, we are placing it aside of macro. So, by doing this does our DRC get violated? Thanks
@@TeamVLSI I watched that video sir, in that you said like in next video I posted how to use these cells in reducing ir drop issue, that's why I am asking sir
Hello Sir, Really pleased to watch the videos with nice explanation. I had only one doubt. How to calculate the distance between two well-tap cells? I know based on the technology specific guidelines but there should be some baseline equation or theory behind it. Thanks in advance. Tejal.
Hi Sir , I highly appreciate your effort on creating such highly informative videos !!! Thank you I ave a query, why are the tap cells placed in checker board pattern..? Thanks in advance
How this amazing lecture is free. Many thanks to you from Korea
Thanks a lot for your appreciation; Best wishes from India :)
great videos for beginners, well explained.
Great explanation sir🎉❤
best channel for VLSI very well exlained .hats off.thanku so much.keep uploading more on physical design.and if possible plz make video on icc2 tool
Thanks a lot Nikita that you love the content.
We will try to do our best, keep supporting.
You can also visit our blog ( www.teamvlsi.com ) and follow the blog.
@@TeamVLSI sure. thanks again
Superb explanation sir ... Thank you so much
Thanks Daddala! Keep supporting.
Excellent explanation...very useful for entry level engineers....kindly do videos regarding CTS in detail with Innovous or ICC tool
Hi Arun
Thanks for appreciation.
Your suggestion noted.
I will work on that.
Great work. Keep going.👍
Thank you Anoob. Keep supporting...
Excellent
Excellent Sir..Thank you so much..
You are most welcome Subba!! Keep supporting and keep learning :)
Thank you so... Much sir🙏🙏
Most welcome, Sheshadri.
thank you sir, from south koera.
Most Welcome!!!
Well tap cells, endcap cells, tie cells, filler cells these all cells will be included under standard cells or standard cell library right ?
Nicely explained....sir
Thanks and welcome
Sir I wanted to know that how to write script to add end cap cells.?
Plz tell
Hi Adil,
I have added the same in this article:
www.teamvlsi.com/2020/08/end-cap-cell-in-vlsi-boundary-cell-in.html
You can refer the HOW TO PLACE SECTION
Thanks
Hello Sir,
Maximum distance between two tap cells is fixed and follow technology DRC. But when placing tap cells in vertical column and if macro comes in between, we are placing it aside of macro. So, by doing this does our DRC get violated?
Thanks
Generally PnR tools take care of this rule, But yes if these not placed at max distance we need to debug and fix the issue.
thanks a lot sir....
Welcome @Kshitij
Does well tap cells are placed such that each standard cell will be in contact with one well tap cell?
No, not in that way, tap cells are placed at fixed distances.
How to use decap cells to reduce ir drop issue, can you post video for this sir
Hi Radha,
Watch decap cells on team vlsi.
@@TeamVLSI I watched that video sir, in that you said like in next video I posted how to use these cells in reducing ir drop issue, that's why I am asking sir
@@TeamVLSI thank you for all these videos sir
Hello Sir,
Really pleased to watch the videos with nice explanation.
I had only one doubt.
How to calculate the distance between two well-tap cells?
I know based on the technology specific guidelines but there should be some baseline equation or theory behind it.
Thanks in advance.
Tejal.
Thanks Tejal.
I haven't gone through the equation yet. If I get something related to this theory, I will let you know.
Thank u sir
Welcome!
Waiting for the same
will add next video soon!
Hi Sir , I highly appreciate your effort on creating such highly informative videos !!! Thank you
I ave a query, why are the tap cells placed in checker board pattern..?
Thanks in advance
Checker board pattern provide best coverage of substrate area for taping.
@@TeamVLSI thank you sir