Brilliant - Thank you! Why not use a couple of 245N bi-directional octal trans to define your functions (literals)? A couple of these will give you 4 functions. Just tie the input pins high or low according to your output function. Because these are bidirectional with a direction being defined on pin 1 - you can lay two transceivers down almost aligned with each other. Have the top 4 bits to go to a common 1C0 to 1C3 '253 bus' and the bottom 4 bits go to a common bus for 2C0 to 2C3. Use a 138N or similar to select which transceiver (function) to use and an inverter on the HC253 G lines to select the 'top' or 'bottom' function. I noticed the HC253 has a tristate output. Could anyone advise me if 74LS153Ns will be OK? These give a LOW output if not selected.
That ALU seems more feature rich than I was expecting, the Manchester Baby just did subtraction and negation. Conditional branch was skip next instruction if zero. The Baby was considered Turing complete afaik.
Interesting project. Nice to see computing reaching the stage of other interests, like woodworking, where you redo old fashioned work for the fun of it.
Julian, I have been watching with great interest the video's about building a (breadbord) microprocessor from you (I also have seen info about this topic from several other makers). I noticed you are (or where) in the design stage of the ALU and taking decisions on what operations to implement and I like to share some thoughts. The registers do not need to be the same size as the 8 bit bus. With 16 bit registers you can do 16 bit operations more easy. Imagine what you can do with 32 bit (4 byte) registers: With three 4 byte input registers (X Y Z) and (for the result) one 4 byte output register (R) instructions could be: - move the result R to one of the input registers X Y Z - add the 3 registers and put the result in the output register R - set a bit in R choosing it from Y or Z depending on the bit in X - set a bit R depending on the majority of the three input bits in X Y Z - rotate by 2,6,11,13,22,25 bits. (Hard wire the rotate instructions so they can be done in less clockcycles than x times shifting one bit) Why these instructions? They are used to to do the SHA-256 hash function used in encription and Bitcoin mining. I expect the hash rate would be to slow to do real mining but it could make the project even more interesting. For details read the article gizmodo.com/mining-bitcoin-with-pencil-and-paper-1640353309 carefully. The diagram is only one round of many cycles in the SHA-256 algorithm. (If it was to easy someone else would be already very rich.) ( If i go to fast this point come back later to read more thoughts shared in this comment: Also include a rotate by -1, 1 and 8 bits. THe rotate by one makes the instruction set more complete. The 8 bit rotate can be used to reach fast the higher bits in the 32 bit registers if only the lowest byte of a register is interfaced to the 8 bit databus. Add instructions to move X to R, Y to R, Z to R and only interface the lowest byte of R. ). Can't wait to see the follow-up in your Computer series!
Very interesting. You are thinking along the very same lines I was thinking of when reverse engineering the 74181. By the way, you can implement a shift right and you get rotators as a benefit on the side. To rotate left, shift left and add the carry back in. To shift right, rotate left 7 times.
6502.org provided lots of inspiration for this. I might have a select line for shift or rotate. Arithmetic shift/rotate through carry may be more tricky.
just getting into Raspberry and ardunio and came across this. can't wait till its finished. hope you are going to make a full list of parts needed to build it myself. please hurry with the next instalment.
Julian, you should run Geekbench 4 on this 8 bit computer you built. How many cores does it have? Who knows, you may have an Apple A11 Bionic killer on your hands.
An arithmetic unit will give a known output for any given input. Presented with an input consisting of 2x8 bit numbers, 1 bit carry and 4 bit function it will give an 11 bit output consisting of 8 bit data, carry, zero, ovrf. A 16 bit 2MWord EEprom when programmed correctly will give exactly the same result. The 21 inputs are the address lines, 11 bits of the output are the data and flags. Functions can even include ROL, ROR,ASL,ASR,INC,DEC as well as the normal add/subtract. These EEPROM can be picked up on ebay for a few dollars. Why make life complicated.
Julian Ilett, using a multiplexor makes even more sense over a ROM when you consider that the ‘instruction’ is simply the pattern/data that the ROM would be holding at the location(s) pointed to by the ‘function’ address lines anyway. Doesn’t stacking the 253s then mean that the data lines would then terminate across all of the layers (2 pins from each 16 pin layer need a 90deg header?)
Instead of stacking multiplexers, I'd just burn an eprom, with all of the address inputs being the function you want plus the data of at least one of the operands, then you get what you want by simply reading it... Oh, and if you're moving away from TTL and going completely to CMOS, then it's not Vcc, it's Vdd! :-)
Dear Julian, I like your very clever solution to the selectable logical function using multiplexers. The multiplexer input pattern could also be encoded using function selection lines and a bunch of diodes. I think this would give a nice retro-fashion style :) Can't wait to see the follow-up !
As HC253 chips are still available as 16 pin DIP wouldn’t it be easier to stack them in that form factor rather than SOICs etc? Neat idea to use them like this BTW!!!
Interesting idea for an ALU, however, I think it may be overly complicated. If you are willing to get rid of a few operations (which can be done in multiple steps), you can reduce your design to being an A/0 mux on the A input on the ALU, and your 4/1 mux on the B input as you had designed. You can even replace the A/0 mux with a simple 8-bit and gate, where if you pass 1 as the input, you get A, otherwise you get 0, since every operation you listed (including in your following video) can be done in either a single configurable truth-table, and an A/0 mux. As an aside, this is exactly how FPGAs and CPLDs work, being mostly composed of muxes (usually 4 to 1 and 2 to 1), and the truth-tables are populated when the device is programmed and stored in SRAM. With that said, even though you wanted to avoid programming parts of the design, it might make sense to use a CPLD for your ALU (there are some breadboard breakout designs - I found some for the coolrunner with a quick search). It would allow you to consolidate the adder, and the muxes into a single part. If you decide to use a CPLD, and want some help programming it / writing the HDL, let me know. A final comment about your ALU, you might want to also add an output zero test, could be useful for testing if A > B, etc. You can do that with a big 8-input NOR gate.
Julian, the 74HC253 is configured such that the SELECT inputs (A and B) are shared by both 4-1 mux channels. Does this not mean you'd need 8 chips total since you can only make use of one chip per bit? Edit: Ah actually you're planning two logic units with the same A and B inputs, so you can use one half of each chip per LU for 8 chips total, 4 per LU.
Julian...if you use Subtract and branch if result is less than or equal to zero also known as SUBLEQ....then a one instruction computer is Turing complete. There is even an OS for such a computer. It is very interesting working out how to do various things with just SUBLEQ.
I know someone who is planning to build a subleq machine. A one instruction set computer where the only instruction is "subtract and jump if less than or equal to zero" (subleq). It's demonstrably Turing-complete.
It sounds like you're going for a Harvard Architecture, which is fine...not my preference, but it's your computer. I do have some suggestions. First off, have each ALU function be its own contained "chip" or box. So one box that does addition, one for multiplication, one for exponents, one for division, and one to convert to 2's complement. This way, you'd put your operands on the bus, latch them in and then have an OP code line for your actual instruction which forwards the data to where it needs to go. This also allows easily allows you to put literals in. To do that, you can just store it in a fixed location (i.e. address 0x0000 = 0 and 0x0001 = 1) that is a super easy thing to just put in an eeprom and when you reset, you reset to a different default address. Another alternative is to have an increment OP code for your ALU. That said, I can't think of a reason to have a "add 0" because it is basically a NOP, but if you have a reason, then by all means go for it. For your addition a naive ripple-carry adder is fine for this pet project, but if you want to optimize, then look at a carry-skip adder: www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_cska Although, that is probably too much for the general audience. It took me a while to understand it.
just get the thing adding first I'll give you 3 years to do it, then you can 'add' the extra functions later think about what instructions you want first then build the hardware/logic around it
First it appeared to me as a bit of a black box, then I realized it's a black adder.
Oh you
Ha!
It's okay, he has a cunning plan!
I never realised you could do that with multiplexers! Thanks for the info, Julian :-)
and so do i...............
YES! Thank you! More of these please
ALU Man this reminds me of my first year in computer science.
You mean ones complement AND set the carry in. Twos competent already has the “1” added in.
Very nice as always Julien!
Have considered using GALs for address decoding or maybe ALU type functions? Need help in this area :-)
Brilliant - Thank you! Why not use a couple of 245N bi-directional octal trans to define your functions (literals)? A couple of these will give you 4 functions. Just tie the input pins high or low according to your output function. Because these are bidirectional with a direction being defined on pin 1 - you can lay two transceivers down almost aligned with each other. Have the top 4 bits to go to a common 1C0 to 1C3 '253 bus' and the bottom 4 bits go to a common bus for 2C0 to 2C3. Use a 138N or similar to select which transceiver (function) to use and an inverter on the HC253 G lines to select the 'top' or 'bottom' function. I noticed the HC253 has a tristate output. Could anyone advise me if 74LS153Ns will be OK? These give a LOW output if not selected.
That ALU seems more feature rich than I was expecting, the Manchester Baby just did subtraction and negation. Conditional branch was skip next instruction if zero. The Baby was considered Turing complete afaik.
Interesting project. Nice to see computing reaching the stage of other interests, like woodworking, where you redo old fashioned work for the fun of it.
Julian,
I have been watching with great interest the video's about building a (breadbord) microprocessor from you (I also have seen info about this topic from several other makers). I noticed you are (or where) in the design stage of the ALU and taking decisions on what operations to implement and I like to share some thoughts.
The registers do not need to be the same size as the 8 bit bus. With 16 bit registers you can do 16 bit operations more easy. Imagine what you can do with 32 bit (4 byte) registers:
With three 4 byte input registers (X Y Z) and (for the result) one 4 byte output register (R) instructions could be:
- move the result R to one of the input registers X Y Z
- add the 3 registers and put the result in the output register R
- set a bit in R choosing it from Y or Z depending on the bit in X
- set a bit R depending on the majority of the three input bits in X Y Z
- rotate by 2,6,11,13,22,25 bits. (Hard wire the rotate instructions so they can be done in less clockcycles than x times shifting one bit)
Why these instructions? They are used to to do the SHA-256 hash function used in encription and Bitcoin mining. I expect the hash rate would be to slow to do real mining but it could make the project even more interesting. For details read the article gizmodo.com/mining-bitcoin-with-pencil-and-paper-1640353309 carefully. The diagram is only one round of many cycles in the SHA-256 algorithm. (If it was to easy someone else would be already very rich.)
(
If i go to fast this point come back later to read more thoughts shared in this comment:
Also include a rotate by -1, 1 and 8 bits. THe rotate by one makes the instruction set more complete.
The 8 bit rotate can be used to reach fast the higher bits in the 32 bit registers if only the lowest byte of a register is interfaced to the 8 bit databus. Add instructions to move X to R, Y to R, Z to R and only interface the lowest byte of R.
).
Can't wait to see the follow-up in your Computer series!
Very interesting. You are thinking along the very same lines I was thinking of when reverse engineering the 74181. By the way, you can implement a shift right and you get rotators as a benefit on the side. To rotate left, shift left and add the carry back in. To shift right, rotate left 7 times.
6502.org provided lots of inspiration for this. I might have a select line for shift or rotate. Arithmetic shift/rotate through carry may be more tricky.
Can u tell me what are the components required for this project
just getting into Raspberry and ardunio and came across this. can't wait till its finished. hope you are going to make a full list of parts needed to build it myself. please hurry with the next instalment.
Julian, you should run Geekbench 4 on this 8 bit computer you built. How many cores does it have? Who knows, you may have an Apple A11 Bionic killer on your hands.
An arithmetic unit will give a known output for any given input.
Presented with an input consisting of 2x8 bit numbers, 1 bit carry and 4 bit function it will give an 11 bit output consisting of 8 bit data, carry, zero, ovrf. A 16 bit 2MWord EEprom when programmed correctly will give exactly the same result. The 21 inputs are the address lines, 11 bits of the output are the data and flags. Functions can even include ROL, ROR,ASL,ASR,INC,DEC as well as the normal add/subtract. These EEPROM can be picked up on ebay for a few dollars. Why make life complicated.
Yes, it did occur to me that a ROM could do the same job, but I'm keen to avoid the use of components that have to be programmed.
Julian Ilett, using a multiplexor makes even more sense over a ROM when you consider that the ‘instruction’ is simply the pattern/data that the ROM would be holding at the location(s) pointed to by the ‘function’ address lines anyway. Doesn’t stacking the 253s then mean that the data lines would then terminate across all of the layers (2 pins from each 16 pin layer need a 90deg header?)
Instead of stacking multiplexers, I'd just burn an eprom, with all of the address inputs being the function you want plus the data of at least one of the operands, then you get what you want by simply reading it...
Oh, and if you're moving away from TTL and going completely to CMOS, then it's not Vcc, it's Vdd! :-)
Dear Julian, I like your very clever solution to the selectable logical function using multiplexers. The multiplexer input pattern could also be encoded using function selection lines and a bunch of diodes. I think this would give a nice retro-fashion style :) Can't wait to see the follow-up !
As HC253 chips are still available as 16 pin DIP wouldn’t it be easier to stack them in that form factor rather than SOICs etc? Neat idea to use them like this BTW!!!
Interesting idea for an ALU, however, I think it may be overly complicated. If you are willing to get rid of a few operations (which can be done in multiple steps), you can reduce your design to being an A/0 mux on the A input on the ALU, and your 4/1 mux on the B input as you had designed. You can even replace the A/0 mux with a simple 8-bit and gate, where if you pass 1 as the input, you get A, otherwise you get 0, since every operation you listed (including in your following video) can be done in either a single configurable truth-table, and an A/0 mux.
As an aside, this is exactly how FPGAs and CPLDs work, being mostly composed of muxes (usually 4 to 1 and 2 to 1), and the truth-tables are populated when the device is programmed and stored in SRAM.
With that said, even though you wanted to avoid programming parts of the design, it might make sense to use a CPLD for your ALU (there are some breadboard breakout designs - I found some for the coolrunner with a quick search). It would allow you to consolidate the adder, and the muxes into a single part. If you decide to use a CPLD, and want some help programming it / writing the HDL, let me know.
A final comment about your ALU, you might want to also add an output zero test, could be useful for testing if A > B, etc. You can do that with a big 8-input NOR gate.
Fascinating mate.
Cheers David :)
Are you going to do the Christmas tree kit build live stream this year?
Do those LED strips have internal current limiting resistors?
Julian, the 74HC253 is configured such that the SELECT inputs (A and B) are shared by both 4-1 mux channels. Does this not mean you'd need 8 chips total since you can only make use of one chip per bit?
Edit: Ah actually you're planning two logic units with the same A and B inputs, so you can use one half of each chip per LU for 8 chips total, 4 per LU.
Julian...if you use Subtract and branch if result is less than or equal to zero also known as SUBLEQ....then a one instruction computer is Turing complete. There is even an OS for such a computer. It is very interesting working out how to do various things with just SUBLEQ.
_starts thinking about using the 8 line de/mux chips as three input logic gates_
you can use fewer mux chips at the cost of some speed.
reg => mux -> mux based "gates" -> shift reg => alu
are literals really needed? cant you write it something similar to the jump instruction chip, more videos on this computer plz
Can't you just not have a instruction executed only when some flag are set? Then you can inhibit next execution, depending on a flag.
You can decrement by adding 1`s for example :
010 (2)
+
111
_____
001 (1) and carry 1
Ah yes, that's what I was trying to say. And the logic unit can produce an 'all 1s' output. Cheers :)
Only 1 instruction? How RISCy can u get? :D
Yes, this is a super RISC machine :)
So long as you don't byte off more than you can nibble, those bits shouldn’t be too RISCy.
*slowclap*
I know someone who is planning to build a subleq machine. A one instruction set computer where the only instruction is "subtract and jump if less than or equal to zero" (subleq). It's demonstrably Turing-complete.
Julian where do you find that nice wires for breadboard ?
At 0:11 the wire packet label shows mechatronics-onlineshop.co.uk which appears to redirect to an eBay user called "mechatronics-online"
Interesting project! :-)
Name of that led
where do you get those wires? what are they called?
It sounds like you're going for a Harvard Architecture, which is fine...not my preference, but it's your computer.
I do have some suggestions. First off, have each ALU function be its own contained "chip" or box. So one box that does addition, one for multiplication, one for exponents, one for division, and one to convert to 2's complement.
This way, you'd put your operands on the bus, latch them in and then have an OP code line for your actual instruction which forwards the data to where it needs to go. This also allows easily allows you to put literals in. To do that, you can just store it in a fixed location (i.e. address 0x0000 = 0 and 0x0001 = 1) that is a super easy thing to just put in an eeprom and when you reset, you reset to a different default address. Another alternative is to have an increment OP code for your ALU. That said, I can't think of a reason to have a "add 0" because it is basically a NOP, but if you have a reason, then by all means go for it.
For your addition a naive ripple-carry adder is fine for this pet project, but if you want to optimize, then look at a carry-skip adder:
www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html#fsa_cska
Although, that is probably too much for the general audience. It took me a while to understand it.
Very interesting thanks for sharing
Can it play the remix boots and pants song which is: 1 & 0, 1 & 0, 1 & 0.....
Great video. Keep it up.
Paralleling outputs on logic gates is probably a bad idea, since one chip is driven high while the other one is low. Just a hint .. Cheers
Yeah, you'd only do it with open collector or tri-state outputs
No opcodes, why?
Mainly because I want a low part count.
How the hell do you understand all this. The bit I understand is that the torch belongs to you. :)
yeah beats me bud
Please provide me with the schematic. I need it
you dont need jmp to be turin-complete. The mov instruction is turin-complete by itself.
But you do need a g to make turin-complete Turing-complete.
Wow I am surprised that no one has asked if it can "run crisis" the viewers must be smarter hear.
Holy crap, look at this 8bit computer this guy designed. g_ZaioqF1B0
LMAO, what a mess of wires and I'm surprised it works.
just get the thing adding first
I'll give you 3 years to do it, then you can 'add' the extra functions later
think about what instructions you want first then build the hardware/logic around it
Sorry Julian, but are you saying 'literal', 'littoral', 'litrel' or something else? And what are they, please? That's where you lost me. Thanks.
Literal. A literal value. A number. Not just whatever is currently stored somewhere.
Not exlusive OR is XOR.
Nuts n Proud NXOR == XOR?
No...XOR' matches only on X'Y' || XY.
XOR matches on X'Y || XY'
It's no good,.....Windows 10 will never run on that
Does Windows 10 run reliably on _anything_ ?