Electronics Interview Questions : Static Timing Analysis : STA Part 3

[@praveenmukkiri6374]

hi sir, Thanks for such a wonderfull explaination, Hoping for the review of my answer
1)27ns
2)I will add some buffers of arround 5ns to the output of comb(5 ns) and then it will be the input for a mux which selects the output of comb(10ns), now from then again one more mux to select output of last comb(10ns),
so my final Tmin would be Tcq+5(comb1)+5(extra buff)+1(mux)+1(mux) +(setup time)= 14ns

[@ayushgemini]

I am also getting same answer

[@LakkisettyPrudhviraj]

1) 27ns 37.03 MHZ
2)17ns 58.8 MHZ

[@agarwal30deepak]

Delay of MUX is missing in ans2

[@kamleshr2130]

Awesome technique. Thanks a lot !!

[@TechnicalBytes]

My pleasure!

[@breathemusic5260]

Sir what is the source of your questions on digital design and STA?

[@Placement_]

Correct Ans for Last Question 2nd part is 18 ns second only becoz in Question it is clearly mention that only 1 bit input line is only between those Combinational blocks which have 10ns delays So I don't understand why you people are assuming every line as 1 bit line.

[@alvinaug3844]

1) 27 ns
2) 18ns

[@shri1527]

can we further increase the time period by putting an extra flipflop in between CL1 and CL2 ?

[@TechnicalBytes]

No dear, we can not put flip flop .. i have given practical example of combinational duplication in the following video:
ua-cam.com/video/gN0eSum4S4E/v-deo.html

[@TechnicalBytes]

please let me know if it answered your question

[@TechnicalBytes]

in this example, i have taken a adder.. all its inputs reach at the same time and we need its output at the same time.. In rpple carry adder, carry propagates to the next position, if we put a flop then we can not get the output of adder at the same time.

[@balasubrahmanyamp6406]

@@TechnicalBytes sir i am getting 14ns is it correct.... thanks in advane

[@kiran7264]

For the first question, Shouldn't the first answer be:
Tcq + Tcl1 + 1ns (because of Assumption1 for cl1) + Tcl2 + 1ns (because of Assumption1 for cl2)+Tsu
1+ 10 + 1 + 10 + 1 + 1 = 24ns

[@s02tambe]

Q1. min time period = 27 ns
Q2. min time period(after CL) = 18 ns (if mux propogation delay is considered to be 1 ns)

[@TechnicalBytes]

Very nice .. Probably, you have replicated one of the CL of 10ns. You can reduce minimum time period further by replicating another 10ns CL logic. Please reply, once you are able to reduce time period further..

[@s02tambe]

@@TechnicalBytes Sir, not sure whether I am right. min time period (after replicating three CL) = 5 ns. We will require two 2X1 muxes and one 4X1 mux. Assuming each mux is having propagation delay of 1 ns. 2X1 mux for 5ns logic, 4X1 for 10 ns logic as we are having two input coming to that combination.

[@TechnicalBytes]

@@s02tambe can you draw your answer on the paper and share it with me by putting it in any share drive like google drive..

[@TechnicalBytes]

@@s02tambe I will review it .. and let you know .. We really appreciate your interest.

[@s02tambe]

@@TechnicalBytes Thank you sir..

[@winself]

superb question !

[@TechnicalBytes]

Thanks !!!!!

[@ujjwalkumar7199]

sir please tell the answer...my exam is on 25th..

[@TechnicalBytes]

one of our subscribers tried to solve it like this, but it is not correct.
drive.google.com/open?id=1WoD_-X1DTu0UxibiOLkRhvAfCOJHPxRL

[@placementdas3997]

@@TechnicalBytes Sir here he is assuming that the delay for both 2X1 and 4X1 mux is 1 ns. But a 4X1 mux is made of 3 2X1 muxes so delay will be atleasr 2 ns

[@jeettirkey7948]

@@TechnicalBytes thank you sir such a GOOD content

[@Placement_]

@@TechnicalBytes Correct Ans for Last Question 2nd part is 18 ns second only becoz in Question it is clearly mention that only 1 bit input line is only between those Combinational blocks which have 10ns delays So I don't understand why you people are assuming every line as 1 bit line.

[@ayushgemini]

@@TechnicalBytes I think Its wrong. Correct answer is 14ns. By using two 2:1 MUX

[@SowjanyaRath]

solution please

[@kiran7264]

Answer for Question for viewers:
Ans1: Tmin = Tcq + 10 ns + 10 ns + Tsu
Tmin = 1+10+10+1 = 22ns
Ans2: Tmin = Tcq + 10 ns + Tmux + Tsu
Tmin = 1+10+1+1 = 13ns

[@faneeshbansal]

wrong ans, as we have to select the critical path ( path which has maxm delay) to find the maxm frequency so that each register to register can work without any timing error.

[@shrikantbhise3176]

Q1: 27ns
Q2: 14ns

[@kaustubhmane4304]

13ns