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Dynamic Random Access Memory (DRAM). Part 1: Memory Cell Arrays
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- Опубліковано 6 сер 2024
- This is the first in a series of computer science videos is about the fundamental principles of Dynamic Random Access Memory, DRAM, and the essential concepts of DRAM operation. This particular video covers the structure and workings of the DRAM memory cell. That is, the basic unit of storage capable of storing a single binary digit, a 1 or a 0. You will see that a DRAM memory cell is comprised of a single pass transistor connected to a single capacitor. You will also see the way that these cells are arranged in a large rectangular array connected by thousands of bit lines and word lines. In addition, you will learn about the role of differential sense amplifiers when it comes to reading and writing data to such an array. In the videos that follow, you will find out more about the way DRAM cells are addressed, and how they are organised, so that it is possible to store bytes and words rather than just single bits.
Perfect tutorial! You sir are the rare 0.0000000000000000001% of the population that can explain things properly!
You are very kind :)KD
Yes, very rare and quite wonderful.
Because you come from a software background I assume
"You sir are the rare 0.0000000000000000001% of the population"
Did you fail math? Or do you know of trillions and trillions of people the rest of us don't?
@@TonyTigerTonyTiger He has simulated reality multiple times and observed that in million million million people thus there will be only 1 person like computer science
Thank you so much for the great series on DRAM!
Great video. I got it right away. Listening to Steve Wozniak talking about when DRAM started appearing and how they chose to go with it because it was cheaper, and how it had to be refreshed all the time, got me interested.
one of the best explanation videos I've seen in a while.
This is much better and clearer than my prof's explaination, great work!
this channel have really really informative videos, please keep up with the good work, your explanations are perfect
Without any doubt this is the best video on the internet about DRAM. I salute you sir
You are too kind. :)KD
love how you start at the lowest level of abstraction and work your way up. Makes this content super digestable :)
I really can't thank you enough for this clear and comprehensive explanation
I cannot believe that this channel has that number of subscribers. It worths definitely thousands more than that. Well, thanks for this video i wish that u would be my prof...
An excellent lecture that very clearly explains the structure and principles of a dynamic memory. I wish you will continue to do so for the benefit of humanity and especially for students and engineers who want to know better and understand the principles perfectly.
You are very kind. I am currently working on videos about GPUs and the graphics pipeline, quantum computers and an introduction to programming with VB.NET :)KD
00:40 : What is a memory cell and how is made?
3:50 : How are memory cells arranged together?
4:21 : How can you read the content of a cell?
8:25 : Why so much work for just reading a cell? Eheh
9:27 : Summary!
I appreciated the video 🤙
Thank you :)KD
Thank you so much for being alive in this world to help me understand how it work , best wish for you and your family.
Thank you 😊😊😊:)KD
This series is beautifully done. I can only imagine the amount of work to create it.
One point of correction is at 9:21 refresh interval is stated to be 64 ns, but should be 64 ms.
Thanks for the lovely comment. I double check for errors. :)KD
This explanation is what I’m looking for, great man !
Delighted to help :)KD
very well explained, thank you! looking forward for your other videos.
Thank you :)KD
this is the best i have seen for dram working explanation !!! Thanks a lot for this detailing out in a understandable way !!!
You are most welcome :)KD
Nice and clear explanation for DRAM! Thanks a lot.
You're most welcome :)KD
Great job, sir. Thank you so much for this content!
You're very welcome, and thank you :)KD
you did what google or wikipedia couldn't do in 2021, respect for you sir.
Thank you!!! You make my Computer Science book must easier to understand. What I most appreciate about your video is the information is absolutely relevant to what I am reading in this dumb book.
You are very welcome :)KD
This is number one explained video on this top.
Sir, Lot of love from Bangladesh
Think about the sheer amount of knowledge involved in our digital world, all start from a transistor.
Indeed. :)KD
@@ComputerScienceLessons you have mind-blowing series Thank you for all your videos I wanna see your face and I wanna know you more elaborately
3:05 "When the gate is closed..." that will happen only if voltage is applied to the Gate. But here terms are opposite as in a normal circuit switch. Also thank you for these wonderful tutorials.
Interesting video for people who wants to know more how things works.
Very good, well done !
this was great. way better job then my Prof. Thank you!
You're very welcome :)KD
Very clear! Thanks a lot!
You are most welcome :)KD
Wow!, You've earned yourself a subscriber here. :)
Glad you like. Thanks for the comment. :)KD
Excellent explanation ❤️❤️❤️
Really Amazing Video ... Kudos!
Thank you :)KD
Very understandable. Thank you.
Best Tutorial ever. Thanks
Thank you :)KD
Awesome, I can easily understand the flow of the principle. Thank you for producing the tutotial of this topic. Any Engineer should know the foundation how memory DRAM works when it comes to read and write. Looking forword to finish the rest of the videos in the series.
You're welcome. I will be revisiting this series soon :)KD
The retention time should be 64ms, instead of 64ns. This is really a great video!!!
Perfect video :)
it's perfect video with perfect explanation!!
Thank you :)KD
Excellent series sir.. the most required one. If you could add the differences between various ddrs it would be very helpful
You are very kind. I will return to RAM one day :)KD
Thank you so much! this is great
You're very welcome :)KD
Sir you are awesome
Thank you Sir !
This is excellent
thank you teacher !
An amazing tutorial you are great.can you please explain how to Initialization, Calibration, and Training the dram
Thank you so much.
You are most welcome :)KD
This is so good, I feel like God guided me here.
:)KD
what is the sequential order to watch your videos? I want to learn about computer architecture from starting so have you uploaded other prerequisetes videos?
Just wow!!
Thanks :)KD
Thanks bro
Great series, sir! Although i have one question... At 6:26 didn't you mean the charge would move from the WORDline onto the capacitor? Since the partially charged wordline is connected to them, not the bitline.
Hello thank you sir.
Hello. You are welcome :)
thanks!
Excellent explanation!!! I've never seen a more didactic video on this matter. I would like to ask you, which book do you recommend me to read, to learn more about the electronic behavior of computer components. I am a Mechanical Engineer with little understanding on these topics but I would like to learn more. Thanks!!!
You're very kind. Thank you. I honestly can't recommend a book because I didn't use one for the DRAM series (but I am sure there some good books out there). I did most of my learning for this online; reading websites and articles, and watching other people's videos. I double, triple and quadruple check anything I learn, dig around to fill the gaps in my understanding, and consult other people on the excellent stackexchange.com I made this series because I wanted to explain to my A level computer science students why it takes the same amount of time to access any element of an array if you know the index number. :)KD
@@ComputerScienceLessons Thank you very much for the reply!!!
Sir can you help me regarding how byte addressable vs word addressable dram would work?
Do the word line and bit line have anything to do with the rows and columns of actual DDR SDRAM? In a x16 device, there are supposed to be 16 cells in a column -- how is this reflected in the topology of the cell array?
Your voice rings a bell. 😊. That physics channel. Right?
Not me, but my brother has a Physics channel and we sound similar. :)KD
Using transistors and capacitors from an electronics kit, could I build 2 bit dRAM using this method? And if I felt up for the challenge, would it be possible to scale it up for like 100 bits? I love building electronics and am fascinated with how computers process 1s and 0s
You could indeed, theoretically, but you might have to burn out a few components on the way. You might find this website interesting. ua-cam.com/users/eaterbc
Please can you explain to me how we determine the value of the bit for one particular memory cell, I did not inderstand very well How this Works. Thanks very much.
9:20 refresh operations occur approximately every 64ms as defined by JEDEC standard, not every 64 nanoseconds
How long a second is😮😮 really great tech
This is great tutorial. But it is not clear why precharging bitline is necessary. Also not clear is why the voltage on it changes by only a small amount (near 6:10) \delta{V}. Is it because the time duration for which the pass transistor is ON too short? thanks
Why did you make Part 2 private ? It's a great video which helped mi a lot in understanding of RAM.
I wasn't happy with the quality. New version on the way soon. KD
Sir in the beginning you mentioned that the value of capacitance is 30fF ..Sir what technology did you refer to 65nm or 90 nm?
3:33 but single fet transistor can only pass current in one direction drain to source ( forward bise ) . Then how same can do the reverse ??
Great question! These are actually symmetric devices and don't actually have a drain or source, or you could say the drain and source switch between reading and writing a 1 or a 0.
Thanks for the amazing content!
There's one thing I don't get. Why should the cells containing 0 should be recharged? If, after all, they are not charged hence representing 0
Because they are floating, depending on the state of the other cells around them they can leak up to a 1.
❤️
😊 :)KD
Is each row or column a memory address in the 2D array?
Are bitlines disconnected from ground by the sense amplifier?
No, during precharge they are "equilibrated" to an "equilibration" voltage that is a sort of halfway voltage as mentioned.
If I understood you correct, you described the bit line both as reading and writing, i.e. discharging and charging the capacitor.
Furthermore this just playing with one of the two bits, the bit 1. And the bit 0 is just there for looks. How that cell is kept out of the way of being detected by means comparing its voltage .... is not discussed at all.
Do you mean to say that in order to charge ( write) the capacitor the gate voltage is lowered and once it is charged the voltage of the gate is kept high?
And since the capacitor is never fully discharged, for it to be charged the bit line of course has to have higher voltage and for it to discharge the bit line voltage has to be lower.
And you haven't mentioned the value of the gate voltage.
And for the capacitor to charge or discharge you have to send current to the gate?
If so then so many cells are connected in a row all them cell's gates are getting current and the 0 discharged cells will get charged for no reason, i.e. being written to while the other 1 bit cells getting read or discharged.
I see some charging ( writing) that has take place in the second row ( the first the the third cell) on the 0 bit cells, while the other two 1 bit cells are showing slight discharge. So I assume that the 0 bit cells in order to be read, some charges are sent there and then immediately has to be discharged somehow.... not sure how that is done. Espcecially if it is ROM memory. It shouldn't be changed.
It seems perhaps you are thinking of the transistors here like BJTs, they are FETs though and no current travels from the gates to the cells.
How the charge is getting transferred for and to the capacitor by applying voltage. i have understood one case that when the capacitor is fully charged and high voltage is applied to gate the charge gets transfer from drain(capacitor) to source (bit line).but how come the reverse is happening means how zero vol capacitor getting partially charged after getting read(means charge is getting transferred from source to drain).could you please explain it sir.
Remember that during the read the bitline is at an in-between voltage. So lower than a charged capacitor but higher than a discharged capacitor. In either case if the transistor is conducting the capacitors move twords that half way voltage.
I saw in another video that DRAM cell refresh interval is 64ms, not 64ns
if BL=1.5V and Vcap=3V, then in reading operation the Vcap will drop to 1.5V, right? How do you do stop Vcap to drop that much?
Early in the video he mentions that reading the cell is a destructive process and what you point out is why. The bitline and cell will share their charge and move to a new voltage slightly offset from where the bitline was. Once the sense amplifiers fire they will pull the bitline back to where the cell was and this will re-charge (refresh) the cell.
what happens in the capacitor whe the gate is closed, does it remains charged or uncharged??
It remains charged, for a while, but the current contents of the RAM need to be refreshed (i.e. capacitors recharged) periodically. :)KD
what type of transistor in used in Dram cells?
These days something like en.wikipedia.org/wiki/FinFET
Excellent video! Clearly explained and illustrated. If possible, I'd only suggest adding a bit of animation. Nothing fancy, just enough to draw the viewer's attention - sometimes it took me a while to actually see what you were talking about.
Fair comment. Thanks for the feedback. :)KD
🤩Wow
Thanks 😳 :)KD
I think the location of source and drain terminals should be interchanged
9:22 the refresh duration should be 64ms instead of 64ns. Am I right?
What happened to them cells with no charged capacitors. The 0 bit cells? How do you read those and why have a capacitor there anyway? Unless it is there just in case you want to change its value, changeable. What about the ROM. Are there capacitors there in the 0 value cells and for what unless it is there to change its value too?
Maybe it is covered the next video.
So far very informative.
This a video about DRAM, as in RAM not ROM. So the cells can potentially be changed from one logical state to the other all the time. So a 1 may be written over to a 0 and vice versa. The 0's are just as important as a 1 as they are both a single bit of information.
Speaking of DRAM, a dram is a unit of weight 1/16th of an ounce or 1/256th of a pound. Please help spread awareness of the dram.
Och aye, the wee dram. But let's not forget that 1 dram = 3 scruples and 1 scruple = 20 grains. :)KD
Same videos for SRAM ? :)
Please prepare a discussion on enterprising
Could you be more specific please?
@3:47 "you can see that 'reading' the content of a memory cell is a destructive process". Why? I understand it would be if you were to replace a 0 with a 1 but not why it would be simply reading the memory cell.
To check if a cell contains a 1, it must be allowed to discharge a little. Similarly, to check if a cell contains a 0 (i.e. to check if it has no charge) it must be allowed to charge UP a little. When a cell containing a 0 charges up a little, it effectively 'destroys' the 0 it contained. Imagine a bucket of water: to check if it's full, you have to pour some water out (so it's no longer full); to check if it's empty, you have to pour some water in (so it's no longer empty). At the risk of muddying the water, it may help to bear in mind that there is a minimum amount of charge, below which a cell can no longer be thought of as containing a 1. Conversely, there is a MAXIMUM amount of charge ABOVE which a cell can no longer be thought of as containing a 0.
In case you are like me.
Making this in "Circuit Wisard" what Transistor do you need? my reset whit backfire power.
So problematic when power open it self, or do other things like open the valve the other way around and other funny problems. No both ways Master Transistor that say: "you shall not pass" when not open. "i can't find the Gandalf Transistor" :-D
And my free version P Ch MOSFET work like N or not working.
"So, Nice VideoFilm About DynamicRandomAccessMemory." Dr.HunterAgoldbi
if the all transistor were to be with one capacitor in 100% voltage and other in 0% voltage, then right now is not neccesary to higthering or lessering that capacitors voltage, but on its output sind capacitor get one switch to be output in cero or higt signal... so the reading or writing are synchronicse with output switch and clock to new data or registres, for that the transistor conmuting to Zero or high level if only signal input is in the shiper instant and about gate diode to be negative or positive voltage to ok output being one 1 or 0 digital binary... so our only get free the rampe clock active with the signal binary, in concluscion we only spend the more lessering 1% energía that other system ram, rom or cpu... esto sumado a la refrigeración líquida obtendremos celulares frías o pantallas frías por láser optico... rendimiento al máximo y velocidades muchos mayores de Ram o rom... 👽👽👽
approximately every 64ms NOT nanoseconds.
I notice that either. According to JEDEC, Memory cell need to be refresh every 64ms. Which mean 16 times refresh operations happen per second for per cell😊
yay i am viewer 7000
It must be my lucky number :)KD
@@ComputerScienceLessons there should be more !
how about static ram
The layout is very similar but the cells are built from logic gates making them non volatile. Therefore the way it works is somewhat different from DRAM. I will cover SRAM in another video. :)KD
ok :)
core memory but its voltage instead of current
😢
mate youve given years of wondering a meaning.
I hope that's a good thing :)KD