The Meeting of the SoC Verification Hidden Dragons

Panel presented at DVCon U.S. 2022
A gap in semiconductor verification has formed between block functional verification and system SoC validation. Gap requirements for large block, sub system and early SoC verification have been extended to include device integrity (cache coherency, security, etc.), together with multi-block and SW functionality. This is at odds with the inability to run high performance random tests on an emulator and the coverage that can be achieved using real world workloads. Multiple methods, some in conflict with each other, are being explored to close this gap that include formal methods, synthesis with Portable Stimulus, improved hardware execution platforms and others. This panel will compare and contrast these methods from different verification viewpoints, hashing out the pros and cons while taking input from the virtual audience.
Moderator: Brian Bailey, Semiconductor Engineering
Panelists: Mike Chin, Intel; Adnan Hamid, Breker Verification Systems; Balachandran Rajendran, Dell EMC; Ty Garibay , Mythic AI
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