Hi Shwetha, Glad to hear my name in this video 😃 I didn't expected this lol 😂. I appreciate your efforts and work. 😇 Thank you very much for you time ☺️ If possible try to give some questions at the end so that we can try to solve them. And in near future videos I am expecting a code execution in tools like vivado or questasim or any other hdl softwares. Good job Shwetha.
Hii Yaseen, It's my pleasure dear☺ Next video will be on practice set only, so don't worry. Actually after complection of 1-2 topics I'll provide some practice set questions. My team is working on code execution videos and will be uploaded soon. Till then u can practice on EDA Playground. Keep supporting ✌✌
really nice explanation mam...thank you so much...please also make videos on verilog coding like spi controller, interrupt controller and sync async FIFO
Hello Shwetha, your explanation is simple and easily understandable. Keep going. Also I have a question that in case equality operators( that is with ===) how can we differentiate logical equality and case equality? In the given examples you have given general equality examples. What are the different examples that proves that logical equality differs from case equality.
Being a signed data type, -10 will be 11010 and shifting right for 3 times will give 11111, then adding 0 will give 11111 i.e. -15. my question maybe wrong kindly explain.
Hii Arya, -10 value will not be 11010, it's correct value in binary is already given. After performing 3 bit arithmetic right shift you'll get 00111...11110 , again take 2's complement of this and you'll get -2. You have little bit doubt in 2's complement concept, kindly revise that dear and then try to solve. Definitely you'll get the answer. Hope this Will help to u.
Thanks @moulik and @vlsi point . If I will take 2's complement then it's fine. But I got confused because in the slide it was written as sign data type, I misunderstood it with signed magnitude representation. Just a small doubt : if I take it as sign magnitude form then my explanation would be correct na ? Hope you will clarify this also
Not necessary but if you know then it'll help to understand the logic. By the way keep watching my videos that is enough for verilog concept understanding.
frequency divider with logic..mod5 use karke f/5 banana using that -ve clk extra ff for delay wala explain plss...also design this with verilog(direct with behaviour ho jata hai wo wala)
Binary sign system works in 2's complement method, 10 (bin 00001010) --2's complement: -10(bin 11110110) after 3 right shift :let x= 11111110 (no carry) so answer is -(2's complement x) =-(00000010) =-2
Hi Shwetha,
Glad to hear my name in this video 😃
I didn't expected this lol 😂.
I appreciate your efforts and work. 😇
Thank you very much for you time ☺️
If possible try to give some questions at the end so that we can try to solve them.
And in near future videos I am expecting a code execution in tools like vivado or questasim or any other hdl softwares.
Good job Shwetha.
Hii Yaseen,
It's my pleasure dear☺
Next video will be on practice set only, so don't worry. Actually after complection of 1-2 topics I'll provide some practice set questions.
My team is working on code execution videos and will be uploaded soon. Till then u can practice on EDA Playground.
Keep supporting ✌✌
Hi @YaseenKhan-ow9sz, Can I get your contact number? Want to discuss some VLSI concepts.
After seeing ur explained style .....I really appreciate you for giving this much good concept in easiest way.
Thanks Om!
Keep watching, Stay connected ✌✌
Best Tutorial so far on UA-cam, Thanks Ma'am
Most welcome Nikhil!
Keep watching✌
Great mam 💞
Really good clarification mam😍
Ma'am pls make more videos. It is too helpful.
Hello mam this Playlist is very nice and easy to understand✨
Very nice explaination thank you so much😊😊
you are a holy blessing in vlsi study point or zone
dil se thankyou😊
Thanks a lot Satyam❤
Very understandable all lectures thank u mam 😊
best videos on vlsi
Good experience to teach thanks
Thanks for Watching
Nice mam your teaching 👍👍
Eagerly waiting for next session.
It'll be uploaded soon.
Thankyou Shweta for this initiative, keep uploading👏
Very nice explaination mam really 💫
Thanks Aniket, Keep watching ✌✌
MAM i am taking coaching in maveen silicon but here explain is nice compare to that I hope i had seen these videos earlier
Very nice video.... keep it up 👍
Thank you so much!
very good experience
Thanks Mohsin!
Very Easy explanation ❤
Nice lecture
very helpful for me thankyou mam
so well explained thank you
Thanks Shubham!
Great effort ma'am keep uploading 😊😊😊😊
Thanks Amar!
Keep watching ✌
Maam U r doing great thing, keep it up for us 💙
Thanks Mam☺..I really appreciate you for teaching 🤗😀
Superb...👌
At 22:20 third wale me 3'b101 me 3'b kaise aaya ?
really nice explanation mam...thank you so much...please also make videos on verilog coding like spi controller, interrupt controller and sync async FIFO
Thanks Abhishek! Verilog coding videos will be uploaded soon. Will try to cover maximum topics, Stay connected ✌✌
Eye opening video for vhdl
Nice explanation mam....truelly appreciable 💐💐💐
Thanks Shivanshu, Keep watching ✌✌
Nice 👍
bahut sahi:)
Thanks for this
❣
Nice explain... 🙏
thank you akka , your doing great
thanks mam you videos to much helpful ... mam plz do videos for system verilog also
Very helpful
Thank you mam !
Thanks yarr 🙌
Thanks for watching!
Stay connected ✌✌
Hello Shwetha, your explanation is simple and easily understandable. Keep going.
Also I have a question that in case equality operators( that is with ===) how can we differentiate logical equality and case equality?
In the given examples you have given general equality examples. What are the different examples that proves that logical equality differs from case equality.
I have explained in the video, the main difference is in case of unknown X . You can watch the video again to get more clarity.
very nice mam
nice mam
Thank you ❤️ mam!..
Medum kuch Axi protocol ke bare me video banaye please
🙌🙌
Please explain how we got the answer as -2 at time 19:44. That may clear many concepts. waiting for your reply.
Being a signed data type, -10 will be 11010 and shifting right for 3 times will give 11111, then adding 0 will give 11111 i.e. -15.
my question maybe wrong kindly explain.
@@aryasingh1861 take 2's complement for a negative number.
Hii Arya,
-10 value will not be 11010, it's correct value in binary is already given.
After performing 3 bit arithmetic right shift you'll get 00111...11110 , again take 2's complement of this and you'll get -2.
You have little bit doubt in 2's complement concept, kindly revise that dear and then try to solve. Definitely you'll get the answer.
Hope this Will help to u.
Thanks @moulik and @vlsi point .
If I will take 2's complement then it's fine. But I got confused because in the slide it was written as sign data type, I misunderstood it with signed magnitude representation.
Just a small doubt : if I take it as sign magnitude form then my explanation would be correct na ?
Hope you will clarify this also
awesome
Very nice .. 💗
Thanks Ramesh!
Keep watching ✌✌
Informative
Hi,
Let me explain shift operation Example no3 in which there is shift operation in signed data types, How the result is -2?
nice efforrs mam
thank you mam
what a great video
thanks mam
Hello mam,
knowing C/C++ is necessary for verilog or not?
Not necessary but if you know then it'll help to understand the logic.
By the way keep watching my videos that is enough for verilog concept understanding.
Thank you so ..much mam for your suggestions and response.🙏
Timestamp: 19:14, suppose x = 4’b1001 hai, to x
0011
is x and xbar same? x.xbar = ?
xbar is negation of x
Hello Shweta how the answer of c=a+(b>>>3) is -2
frequency divider with logic..mod5 use karke f/5 banana using that -ve clk extra ff for delay wala explain plss...also design this with verilog(direct with behaviour ho jata hai wo wala)
In the comment box it's not possible to answer this kind of doubt, you can ask in our telegram group
Good
Thanks Shaista, Keep watching ✌✌
19:50 I'm getting the value 15..
Shifting -10 right side 3 times
I'm nt getting -2
Binary sign system works in 2's complement method,
10 (bin 00001010) --2's complement: -10(bin 11110110)
after 3 right shift :let x= 11111110 (no carry) so answer is
-(2's complement x)
=-(00000010)
=-2
thank you :)
Ma'am it would be very helpful if you could provide these slides as notes.🙏🙏🙏
Yes Nikhil, I am planning to provide notes. It will be available soon.
Stay connected ✌✌
How to solve arithmetic operator question
a=0,b=-10,c=a+(b>>>3) can u explain this mam ,for me its not getting 2...
In arithmetic shift example where A=0, B=-10, How is C=-2?
Mujhe bhi nhi samajh aaya and at 22:18 pr 3rd me 3'b kaise aaya ye bhi explain nhi hua
Even I didn't understand....
Video examples to kai saare the but unka solution nahi karaya acche se so please pay attention to it