Sizing of MOS in CMOS DESIGN BY Sumit Vaish

[@Samur4i_14]

ΑΔΕΡΦΕ ΣΕ ΑΓΑΠΑΩ! ΜΟΝΟ ΕΣΕΝΑ ΚΑΤΑΛΑΒΑΙΝΩ ΑΠΟ ΤΟΥΣ ΣΥΜΠΑΤΡΙΩΤΕΣ ΣΟΥ, ΕΥΧΑΡΙΣΤΩ ΠΟΛΥ!!!!❤

[@sharvaripatil6918]

Really thank you sir for this simple yet easy explanation

[@shivi8774]

Thank you, sir. Really thanks a lot, sir. I was so confused and none of the videos helped but this did...

[@SumitVaish]

Glad it helped

[@tharunprathapan5883]

Simple and easy to understand. Thank you for this explanation sir

[@akhilshetty9924]

u saved my day sir .......u erned my subscribtion.....love u a lot sir

[@vamshidhar517]

nice explanation sir.

[@anvithk6346]

Thank you 😊

[@AdithyaNayak-x4d]

Actually for Pull Up Network n=3. Because for Pmos 2R/n formula. So 2R+2R+2R/3=2R. So n=3.

[@Jinxed192]

But why should we make the resistance R?

[@MOHDMUFEED_]

I confused for pull up i need resultant 2R for each pull up path??

[@faneeshbansal]

Because the mobility of nmos is double that of pmos, so resistance in pmos will be 2R
And always remember, the width is directly proportional to capacitance and inversely proportional to resistance.

[@SumitVaish]

@@faneeshbansal Cool

[@nivedpv2997]

this is wrong method

[@SumitVaish]

I would like to hear from you more. Please guide us where does this method fail.