If you look at the chilli tomato noodle channel, he sometimes explains why a chip (e.g. a CPU) is made the way it is. You have to dig through the correct videos though. At 54 minutes in this example linked video, he explains for instance why you might use tristate buffers instead of multiplexers (or vice versa). Do remember though that the video is a different topic to this one. ua-cam.com/video/ZDMTRyJZE44/v-deo.htmlm50s You can also learn some bits here and there from the Jeri Ellsworth channel. Often, she'll look at array architectures (e.g. fpga) but will use them to mimic a multiplier-tree architecture (like a bog standard CPU). If you look at the books she recommends, you can learn a bunch about Hardware Description Languages (maybe vhdl or verilog). When you come back to it all, it is also worth looking at trigonometry with quadratic equations (teenager maths) which then helps you look at polynomials and then the calculus (before going on to Fast Fourier Transforms). The FFT though can be better understood if you look at animations on how a square wave is made (for your 1's and 0's of machine code used in say _"two's compliment"_ etc). Having to hand a cheat-sheet of logic gates and electronics parts is useful (teenager physics class). The Brek Martin channel has some animations of the Fourier Series which is basically squiggly lines draw by a bunch of unit circles orbiting each other like the sun, earth and moon on a trailing stream of paper, like a seismograph (lol). #TheEarthMoved In reverse, an example of separating a signal into its harmonic series using Fourier Analysis, would be the graphic equaliser on a (e.g. wav file) audio player's LCD screen. You know, like how _"do ray me fa so la ti do"_ notes (Solfège) is the circle of fifths. Then that is put into an array (for x y pixels co-ords etc). You can do it.
@@obsoletepowercorrupts I liked your reply but I also think you missed two very important helpful things. They can also check out 3Blue1Brown for all of the complex maths and Ben Eater for Simple Hardware - CPU design.
The structure you aren't sure about is the ESD protection clamping diodes. From the datasheet: "All inputs are protected from damage due to static discharge by internal diode clamps to Vcc and ground".
Just to think that this is a quad dual input nand gate as a single IC. Just imagine a full Intel i7 CPU... it has millions upon millions of theses to create all of its needed parts such as the clock, cache memory, registers such as program counter, memory address, memory instruction, accumulator, shift registers, status or flags register, the adders and logic units within the ALU, All of the muxes, demuxes, encoders and decoders for the controllers of the data paths etc... The buses are just all of the wires that connects everything... This is considered a simple or elementary logic gate as this is one of the building blocks of logic gates and circuits that lets you abstract away from the transistor level. If you try to get into the metal anymore than this, you would then have to deal with the actual chemical materials themselves and quantum mechanics. Nand gates are popular because you can create all other gates with just nand gates. You can do the same with Nor gates too, however in production it is typically easier and cheaper to use all Nands as opposed to all Nor gates although it can still be done. However, that cost difference between using Nand versus Nor is not real significant and it also depends on the particular application and the overall design of the device that is being created. Now if you start to mix the two with in the same circuitry things become a bit more complex. Then you have to worry about both high and low logic as well as triggering on the rising and falling clock edges to keep track of all synchronous applications as timing and gate propagation is extremely important. But yes as complex as the design looks in this circuit is one of the simplest ICs just as any of the other quad Logic circuits are... I've just started to study this in the past year, self taught and I have picked up a lot of it relatively quickly; however I've always had a strong background of Mathematics, Physics and Science. For the longest time I knew the math and theory, and for the longest time I knew how to build and use computers. When I say build I mean by installing the physical hardware, configuring the bios, install the operating system, needed drivers and wanted applications. I'm also self taught in programming particularly C++ with the focus in 3D Graphics Engines which can range from Game Engine design to Physics Simulation, 3D Terrain Generation and more. I'm also involved in studying Compiler and Operating System design which lead me to get a better understanding of Assembly. This lead me to learn the hardware. From there I then found a Jewel of a series by Ben Eater where you can watch him build an 8 bit CPU on a breadboard. I highly recommend it. More than just that; I'm also into learning other advanced topics such as Hardware Emulation, A.I. and Machine Learning. The highest level of a completed accredited math course that I have is Calculus I. However all of the above requires Calculus II & III, Linear Algebra with Vector Calculus and Analytical Geometry. Probability, Statistics and Logic (Boolean Algebra), Number and Set Theory, Abstract Algebra, and Non Euclidean Complex Algebra and Geometry of Higher Dimensions. It takes a vast wealth or knowledge of all fields of mathematics to apply all of the concepts in both Physics and Chemistry just to make a simple digital electronic switch... Just about everything I mentioned in this paragraph alone is needed if you were to design your own single transistor, never mind an integrated circuit. Then connect a billion of them together to make a CPU, another billion to make a GPU a few million to create your APU or Sound Card. This doesn't even account for Ram, PCI controllers(bridges) networking, interrupts for I/O devices such as mouse and keyboard... Then design the instruction set, convert that to an assembly language with an assembler, use the assembly language to create the C language, use that language to create the Operating System, Micro Controllers and device drivers. Run the operating system and create C++ either from C or Assembly or a combination of the two... Then use C/C++ to create APIs such as DirectX, OpenGL, Vulkan and other libraries and APIs. Then use all of those APIs to create Image and Video Editing Software, 3D Modeling and 3D Scene applications. Then use those applications to build some assets. Then start another project to create your Game Engine to incorporate those assets. Tie them all together into an integrated system. Now design the rules to your games, the levels, stages, the story, user interaction. You can not forget about the GUI part, even rendering or drawing text is no simple process. Now include all of the Physics Engine for doing motion, collision detection, A.I., path finding, scoring system, menus and item lists or inventory. Then integrate all of the sounds for sound effects and background music. None of this is any good if the scene looks terrible so you have to have good lighting so now right all of the shaders to do all of the lighting calculations for reflection, refraction, fog, how shiny or flat the surface looks. You need to calculate all of the normals coming off of the edges, faces and or vertices so that the lighting calculations are correct. This doesn't count for texture mapping... And so much more. So by the time you're done with all of that, you can then sit there and enjoy playing Tetris, Doom, Mario, Skyrim or Crysis... Now when you go to the store and you spend $20 - $70 which may seem like a lot of money, just realize how cheap that is if you had to build your own computer from the transistors up and had to write all of those millions of lines of code. One syntax error and it fails to compile. Other errors and it can fail to link or build. Then it finally runs, until it crashes with an unexpected error, probably because you access an invalid memory address... Back to the debugging board... Ah fixed that crash, but the triangle doesn't look right... or it looks right until it spins then it gets all weird... Going back through the code and dropping in break points... Oh this should of been "+=" not "*=" or this should of been "0.001" not "0.01"... as these are run time errors... I've been studying through vast tutorials only for years and I have followed and even made a 3D Game Engine from Scratch. No copying and pasting. I typed in everything manually as I followed along from either what I was reading or listening to. Hours of writing the code, configuring the build environment and many more hours debugging! But after creating that 3D Engine went on to use that Engine to build a 3D 1st Person Shooter style game and I can still run and play it to this day... No college education just the willingness to want to learn it and to apply it and the dedication to do it! You can do anything you want if you put your mind to it!
@@hullinstruments No problem at all. I am also a member of Stack Overflow and I try to help out others as much as I can with the knowledge that I have. When I first started to learn C++ on my own, the internet was around but it was in its infancy so to speak. This was the transitional era from when it went from Dial Up to DSL-Cable. I graduated High School in 1999 and I didn't start learning C++ until about 2003. Information at that time was there but it was limited and hard to find, also the type of content was very limited too. Most of the tutorials then were all text based, very few images and almost no videos since the data transfer rate through Internet Service Providers was very limited and wasn't very affordable either. Not only that but many of the tutorials that I came across never told you how to set up your environment, never told you how to configure your compiler nor told you which compiler they were using nor what flags. They never told you how to debug etc. They mainly gave you a code snippet for a single function and were expecting you to know how to do it. I'm assuming this because most of those who wrote these tutorials in the beginning already had a degree in Computer Science or Computer Engineering and their articles were probably geared towards those who were in College that had some kind of background in it already. It appeared that they weren't targeted towards complete beginners without any knowledge. There were many challenges in the beginning and a slight learning curve. But with dedication and the willingness to learn it and to achieve certain goals; I was able to apply myself to finish the tasks at hand. Now when I look back at the resources that I had and the limited amount of help that was available to me, I don't mind helping others who are trying to or want to learn. I will be straight up with them and tell them that it is very difficult and that there is much to learn and know, but I will also encourage them to try and stick with it as it can be done as long as they are willing to dedicate themselves to put in the time, energy and effort to accomplish such tasks. It's almost like asking a basic construction person (one who builds houses or small buildings) to learn how to build a bridge then go and build it where that bridge has a very coherent, sturdy and durable design that will last for many years while building it at the most cost effective price.
Spent nearly 10 years performing metal inspect and earlier layer inspects, I wish I would have had a video like this to help me try to discern the topography that I saw. Where were you from 93 - 2013 when I was inspecting this stuff ....
@@TheXGamer969 Well .... when you're fabricating, and I was in the photo resist strip section, you're not looking for "WHAT" is being made you're looking for resist that didn't get taken off before you stick it into a diffusion tube, or an annealing furnace and contaminate 300 other wafers. You looked for incomplete etches or over etches. If you were curious you might stick a lot on a scope BEFORE you strip it just to see where it was being implanted ... Other than that ... No you don't get taught what transistors look like ....
It really isn't done by hand anymore. Most of the time, completely off-the-shelf library blocks are just assembled together and copied a massive number of times. Then you would have input your design constraints and simulate the layout to ensure that all of the timing requirements are being met.
I love CMOS technology! Great for battery powered widgets. Has any one heard of or used RCA's 1802 CPU, a 40 pin DIP? Liked tinkering with that one a lot!
what they have there is a transistor array that lends itself to creation of many different logic functions just by changing the interconnecting metal layer. Searching for B Series CMOS leads to a TI page describing the typical construction of inputs
I would imagine there's a diode to VCC and a diode to GND to protect both over- and under-voltage conditions... That's probably what the second weird silicon thing is
That tan leg next to the pad is indeed a current limiting resistor, probably on the order of 100-200Ω. Next is most likely a zener connected to VCC, protecting the gate CMOS from inputs higher than VCC. Finally, the structure with GND on the inside loop and VCC on the outer. I suspect that's just a zener protecting the gate CMOS from inputs less than GND, but I'm not sure why it's surrounded by VCC. If you look directly above the NMOS unit you labeled Q1, you'll see there's a solid VCC structure there too. Do NMOS structures (where Source is grounded) need VDD (aka VCC) right outside their channel area to deplete it of electrons?
I have a book suggestion for you - this is one that for some reason the NY Times Review of Books missed. Title: Conquering the Electron: The Geniuses...etc. Derek Cheung of Rockwell Scientific, MS/PhD EE Stanford is I think the main author. Particularly interesting are the later chapters that cover the development of the integrated circuit - he does a tremendously thorough and engaging summary of how we got to where we are today rustling these electrons. I have the audiobook and actually that is the version I'd suggest.
38:00 those weird things by the inputs are two diodes each, reverse biased from ground to the signal to VCC. Negative voltages are shunted to GND. Positive voltages are shunted to VCC.
Hi the quick explanation of what Q7/Q8 is with its "floatin" connection is something different.. This is how you create an AND gate in CMOS. @30:33 you can see Q7 from GND (blue) going to what you put in as Q8 (green) that is connecting to n1 (output of the transistor).In between you think you do have floating n4... however what it really is, that you have a single transistor with two gates. Both most be active to conduct GND to Out. So this is both nmos, that means, both inputs (n2 AND n3) must be active to let current pass from GND of Q7 to N1.. So it is actually not two transistors, but a single transistor with two gates and both need to be on to activate the transistor. That is something you can see pretty often on cmos and a very simple way to AND stuff. So as you have dawn out, essentially it is 4 transistors. two of them ORed and two of them ANDed. Due to CMOS they need to have the same complementary setup... Not sure if my explanation was good to understand, but in essence - the current needs to patth both pink gates (N2 and N3) to connect N1 to GND. Also I think it could have been done simpler in the diagram but as the circuit need to support a certain current, a single line Q was not enough, so they needed to double it up in lines.
What are all of those 'bumps' on the metallization pads and traces? I've seen them on other people's die shots as well, and everyone just says that it is dust or contamination from the decapping procedure; but, here I can clearly see that it is only present on the metallized traces... Does anyone have any idea what those 'bumps'/'pits' actually are?
I really like these informative hyper technical videos but i can't stop myself from laughing because you sound exactly like that boss guy from the movie Office Space lmfao.
You got it wrong your pin 1 (VCC ) is actually pin 7 (GND) simply by the fact that it connects outside the chip on the isolated metallic square around it best choice for a ground and that your pin 7 (which is pin 1) connects inside the chip good idea if you want to give power to the innards of a chip :P
Now do an 8086 :D (kidding, please don't; we don't want you committed to an insane asylum as a result). You could try doing something fun like another 74x13 (CMOS 4093) which is the same thing but with schmitt-triggers, or 74x14 (CMOS 4106) which is a hex inverter with schmitt-triggers. I think wither of those would be fascinating. Thank you.
hello sir, I want to ask about the design of chips, graphic cards and other computer devices such as Intel, Arm Bionic chips, Apple, AMD, Nvidia. What software did they use to make it?
@@RobertBaruch Thanks a lot. The author replied to me, it's really a exciting thing. I'm a newbie about the chip and hardware things, I wonder if the video could be more detailed, for example, I guess the picture is a x-ray picture, and the white things in the chip is metal, but I don't know whether the chip has multiule layer, how you know two area are connected, it seems really obvious for you, however, it confuses me. I think if you add those information in the next video, it will attract more people like me, and I think you and this video helps me a lot. As you audiance I really appreciate your work, thanks.
@@赶路人-q1w This was an optical microscope image. There is not much useful colour on Silicon ICs so the images are often black and white at the best available resolution. Search for IC photomicrograph on the net or UA-cam and you will get lots of examples to study.
Is this a regular photograph ? (as opposed to scanning electronic microscopy) If so, how come everything seems so transparent ? Should there not be metallic tracks that ought to be opaque ?
It's a normal photograph through a microscope. The white areas are the top metal layer. You can't see through it but it's probably not completely flat so you can see shadows where it goes over other features. The gray areas are probably silicon oxide which is transparent
Most likely a buffer, something that doesn't change the logic value of the signal, but allows the receiver to draw more current from the output, and it also makes the edges sharper by amplifying the signal.
IIRC, PMOS performance sucks compared to NMOS performance; so a large PMOS has comparable drive ability compared to a smaller NMOS. In fact, if you read the datasheet; the smaller NMOS can pull down harder than the huge PMOS! (NMOS has 0.4V drop while sinking 4mA, while PMOS has a 0.8V while sourcing the same.) And if you're thinking "aren't NMOS and PMOS just mirror images, shouldn't they have symmetrical performance?" -- No, the channel in one is N-type silicon and the other is P-type silicon. Different dopants, different majority carriers, different properties.
Yes it is, but you will need a very good Scanning electron microscope and a team of engineers. We do it at our lab here in Texas and just one portion of a 22 nm processor took 8 months.
@@billjames1953 Good job. Texians are awesome. So, you could see if the Chinese put something queer in a chip? So, electron microscope could read internals? And no light limitations, i guess?
@@nailsaggitarius4212 we reverse engineer chips for either legacy parts that need to be re-made or for patent cases. But if we were asked to look to see if something was added, we could do that, but would need to see the original design.
There are other shapes as well. It all depends on what you are trying to achieve. I have seen a circle with a bunch of finger overlapping it for a multi transistor. I think that was on an early microprocessor.
@@excitedbox5705 Yes, I'm aware that there are different shapes. What I'd like to know is - WHY? How does the shape influence the working of the transistor?
@@bonbonpony My guess is sonething about the capacitances, or about semiconductor's resistance. Doing it in a comb like pattern reduces it, shortening the paths
@@mzflighter6905 If it were about capacitance, combing would _increase it_ if anything, because this means more surface area between the electrodes. But you might be onto something: this comb pattern might increase the length of the gate area between the two other electrodes, meaning "wider doorway" for more charge to flow through (higher currents), but without increasing the overall space the transistor takes on the silicon plate.
@@bonbonpony It is done that way to increase the effective gate width of the MOS transistor, which increases the drive current it can source or sink. It's the equivalent of having one very long finger, but since that's inconvenient, they fold it to make it have a more convenient aspect ratio.
...so I have a blown board which is 3 separate boards that come in a kit, how easy is it to trace power over a board? I get lost once it goes into a chip. Not that we do that stuff, but I’d like to be able to prove the point faster.
Depends on the board. Get a multimeter and it makes the job much easier. I recommend the Aneng Q1 or 8006. They are great starter meters and cost under $30.
could anyone explain why would we even want to connect double inverters? I can't find reason other than adding delay which is usually avoided. Sorry if its an obvious thing I'm still learning this stuff.
Notice the SIZE of Q1 and Q2 (fairly big) and compare them to the SIZE of the preceding inverter (Q3 / Q4)... The Q1/Q2 pair can handle WAY bigger loads (such as you might expect on the OUTPUT of the nand gate). If you were to eliminate the Q3 / Q4 inverter altogether, you'd end up with.... an AND gate.
See my explanation above... The output driver transistors are very large... driving them directly from the small logic transistors would slow the circuit down because of the large gate capacitance. So you have an intermediate inverter that has less gate capacitance than the output driver, but can provide a lot more current than the logic transistors. I've even seen cases with more than two inverters in a row, with each inverter being larger than the previous. (And you need an even number to keep it as a NAND gate rather than an AND gate.)
The output driver transistors are very large... driving them directly from the small logic transistors would slow the circuit down because of the large gate capacitance. So you have an intermediate inverter that has less gate capacitance than the output driver, but can provide a lot more current than the logic transistors. I've even seen cases with more than two inverters in a row, with each inverter being larger than the previous.
There ARE capacitors on silicon!!! A prime example being something like DRAM that has literally BILLIONS of caps. In comparison, this exceedingly 'basic' nand gate doesn't WANT any on chip capacitors. It simply acts like a switch that connects the output pin to either VCC or GND depending upon the state of the two input pins. As MZ flighter mentions, it is very common to place a (small-ish) external capacitor VERY near to and across the power supply pins for decoupling. Such decoupling capacitors act as tiny LOCAL power supplies when the output changes state. (Without decoupling caps, the potentially LONG and winding PCB traces to the power pins can act like inductors that can significantly s-l-o-w down the output switching so it's considered 'good practice [TM]' to include one for each 74xx chip if the board is to achieve the highest possible speeds. Something else to keep in mind is that microchips are comparatively small (by definition). In order to make a capacitor of a 'meaningful' capacitance on silicon would consume a LOT of silicon real estate. IIRC, in the late '60s, Fairchild polled some of their 'bigger' customers asking if they would pay a 'premium' for 74xx chips with 'built in' 0.1uF decoupling caps. Given what has survived today, I assume you can guess what he response was? Footnote: You should take a look at the bottom of a PCB underneath a typical modern / powerful FPGA. It's like a small FOREST of decoupling caps for the various supply rails these things use.
If you look at photomicrographs of switched capacitor filters in ICs (like modem of DTMF chips) you will find capacitors. They are low value so cost a lot of silicon real estate, they are avoided if possible and placed outside.
Why is the layout of a single transistor so complicated? I always thought of a transistor as three blocks of alternatingly doped silicon put together. As far as I understand the green and blue regions at 10:41 are the collector and emitter (or the other way around) of the transistor and the pink/magenta region is the base. Why though are they arranged in this complicated intertwining layout and not, as taught on literally every website explaining transistors, as three blocks next to each other? Three blocks are probably easier to "print" onto the chips than this intertwining pattern, so there has to be a reason for this pattern.
@@excitedbox5705 Yes, of course, but why this intertwining pattern? Seeing how microchips are produced I understand why it is easier to stack layers of silicon on top of each other than next to each other. But why don't manufacturers simply put literally three blocks of doped silicon on top of each other? Why is there this complicated intertwining pattern? Maybe this has something to do with capacitance or resistance?
These are called multi-finger transistors, IIRC their main purpose is to efficiently reduce the physical size of the layout compared with single-finger transistors. Also, depending on the circuit, it can also reduce gate resistances and improve device matching (you can split those transistors into several fingers and put them in a manner to fully utilise the floorplan while still retaining their W/L ratio)
@@sbtjlhw111 Thanks for your great answer, I've definitely got some reading to do now :) And the term "multi-finger" kinda suggests that this "single" transistor (as I have thought about it) really is multiple transistors in parallel, which is kind of obvious now and I wonder how I didn't see that myself :D
The earliest transistors (we're talking way back in the 40s / 50s here) were exactly what you've stated. Three 'blobs'. However, these were Bipolar Junction Transistors (BJTs) rather than the Field Effect Transistors (FETs) that they were HOPING to produce. With BJTs, it's far more difficult to just parallel a bunch together. (It CAN be done and is not uncommon in things like audio power amplifiers, but due to the minute differences between each BJT, it generally requires use of emitter resistors). With MOSFETs on digital chips (where ALL of the devices are implicitly VERY close to each other in temperature etc), it's far more practical to directly parallel them without risking the thermal runaway issues you'd encounter with discrete BJTs BTW, transistors on chips can often get 'weird'. It's not uncommon to see single devices that have MULTIPLE gates etc
A lot of ULA chips were "Uncommitted Logic Arrays" that were connected up according to the customer design using the top metal layer so delivery times were reasonable and test masks could be used to characterise the chip. If you had access to the type of ULA core type and the mask design information you could reverse engineer it just by examining the top metal layer. However none of this information was ever made public and many of the companies no longer exist and the workers have retired it is hard to get official data. So one has to resort to transistor level. With the ZX Spectrum you have a lot of enthusiasts who have worked on the designs for years. There may be a ULA design already out there. With the ZX 81 the ULA is very similar to all the logic chips in the ZX 80 that are now missing as the machines are almost the same with the exception of FAST mode. The Spectrum ULA will also share a lot of similar logic to the ZX8x with colour video managed fully in hardware instead of by the Z80 CPU as in the ZX8x.
@Damion Manuel When I ask if emulation would be possible by reversing schematics, I'm talking about something LESS advanced than the NES. Like a tamagotchi or something.
Many years ago, I worked at a company that did just that. Of course, it was utterly impractical to reverse-engineer a complete CPU, but you could do bits and pieces such as PLLs and other interesting circuits. The technology to reverse-engineer modern ICs is quite incredible.
I always see a lot of 2 dimensional organization... Wonder why the depth has never been truly utilized... Granted this is probably why the newer quantum is layered stacks yet theirs so much space that's not being utilized. Would be an interesting path and routing if a 3D printer is developed to create newer design.
Designers minimize layers because it greatly reduces cost. Also think more layers would also mean it takes longer and would increase manufacturing errors. Sometimes simpler is better!
Would it be possible to reverse TI BQ2040 BMS chip to read firmware from its ROM? The specification is wrong regarding smbus write through function to external EEPROM and it would be interesting to check what is happening.
From the datasheet for that chip, the whole contents of ROM are listed in a table. Maybe it's more useful to have a logic analyzer to check the data and address bus for EEPROM communications.
@@mateijordache1952 The idea is to directly access external EEPROM through smbus without need to dissasemble or direct soldering to eeprom. The function is there but doesn't work as in datasheet so there are something that is not documented. For BQ2060 it works correctly.
Love the video, but Jesus Christ can you mute the audio when you’re speeding through parts? Sometimes you do, and sometimes it’s not even that bad. But especially towards the beginning the loud squeaks are super unpleasant. Like I’m not trying to be petty, but it was a serious problem for me.
I’m glad I stuck through it though, it was really only the first bit and since then I’ve watched probably about another 6 hours of content on your channel. It’s a little above my head but I’m really enjoying it, keep up the good work man.
"Pin 1 obviously looks different"
Y-yeah. Obviously
Pin 1 has its corners cut off. It was pretty obvious to me :)
@@RobertBaruch It took me a minute to see that.
@@RobertBaruch Yeah, i think you mean the pads, not the pins? that confused me too
This video seemed easy but quickly went over my head.
If you look at the chilli tomato noodle channel, he sometimes explains why a chip (e.g. a CPU) is made the way it is. You have to dig through the correct videos though. At 54 minutes in this example linked video, he explains for instance why you might use tristate buffers instead of multiplexers (or vice versa). Do remember though that the video is a different topic to this one. ua-cam.com/video/ZDMTRyJZE44/v-deo.htmlm50s
You can also learn some bits here and there from the Jeri Ellsworth channel. Often, she'll look at array architectures (e.g. fpga) but will use them to mimic a multiplier-tree architecture (like a bog standard CPU). If you look at the books she recommends, you can learn a bunch about Hardware Description Languages (maybe vhdl or verilog). When you come back to it all, it is also worth looking at trigonometry with quadratic equations (teenager maths) which then helps you look at polynomials and then the calculus (before going on to Fast Fourier Transforms). The FFT though can be better understood if you look at animations on how a square wave is made (for your 1's and 0's of machine code used in say _"two's compliment"_ etc). Having to hand a cheat-sheet of logic gates and electronics parts is useful (teenager physics class). The Brek Martin channel has some animations of the Fourier Series which is basically squiggly lines draw by a bunch of unit circles orbiting each other like the sun, earth and moon on a trailing stream of paper, like a seismograph (lol). #TheEarthMoved
In reverse, an example of separating a signal into its harmonic series using Fourier Analysis, would be the graphic equaliser on a (e.g. wav file) audio player's LCD screen. You know, like how _"do ray me fa so la ti do"_ notes (Solfège) is the circle of fifths. Then that is put into an array (for x y pixels co-ords etc).
You can do it.
ObsoletePowerCorrupts wow,!,, simply great explanation
@@obsoletepowercorrupts I liked your reply but I also think you missed two very important helpful things. They can also check out 3Blue1Brown for all of the complex maths and Ben Eater for Simple Hardware - CPU design.
@@obsoletepowercorrupts This is great!
@@skilz8098 Exactly, those two channels are worth mentioning!
The structure you aren't sure about is the ESD protection clamping diodes. From the datasheet: "All inputs are protected from damage due to static discharge by internal diode clamps to Vcc and ground".
Was thinking same
Simple chip? Yeah, that's a lot of work. Thanks for teaching us!
Just to think that this is a quad dual input nand gate as a single IC. Just imagine a full Intel i7 CPU... it has millions upon millions of theses to create all of its needed parts such as the clock, cache memory, registers such as program counter, memory address, memory instruction, accumulator, shift registers, status or flags register, the adders and logic units within the ALU, All of the muxes, demuxes, encoders and decoders for the controllers of the data paths etc... The buses are just all of the wires that connects everything...
This is considered a simple or elementary logic gate as this is one of the building blocks of logic gates and circuits that lets you abstract away from the transistor level. If you try to get into the metal anymore than this, you would then have to deal with the actual chemical materials themselves and quantum mechanics.
Nand gates are popular because you can create all other gates with just nand gates. You can do the same with Nor gates too, however in production it is typically easier and cheaper to use all Nands as opposed to all Nor gates although it can still be done. However, that cost difference between using Nand versus Nor is not real significant and it also depends on the particular application and the overall design of the device that is being created.
Now if you start to mix the two with in the same circuitry things become a bit more complex. Then you have to worry about both high and low logic as well as triggering on the rising and falling clock edges to keep track of all synchronous applications as timing and gate propagation is extremely important. But yes as complex as the design looks in this circuit is one of the simplest ICs just as any of the other quad Logic circuits are...
I've just started to study this in the past year, self taught and I have picked up a lot of it relatively quickly; however I've always had a strong background of Mathematics, Physics and Science. For the longest time I knew the math and theory, and for the longest time I knew how to build and use computers. When I say build I mean by installing the physical hardware, configuring the bios, install the operating system, needed drivers and wanted applications. I'm also self taught in programming particularly C++ with the focus in 3D Graphics Engines which can range from Game Engine design to Physics Simulation, 3D Terrain Generation and more. I'm also involved in studying Compiler and Operating System design which lead me to get a better understanding of Assembly. This lead me to learn the hardware. From there I then found a Jewel of a series by Ben Eater where you can watch him build an 8 bit CPU on a breadboard. I highly recommend it. More than just that; I'm also into learning other advanced topics such as Hardware Emulation, A.I. and Machine Learning.
The highest level of a completed accredited math course that I have is Calculus I. However all of the above requires Calculus II & III, Linear Algebra with Vector Calculus and Analytical Geometry. Probability, Statistics and Logic (Boolean Algebra), Number and Set Theory, Abstract Algebra, and Non Euclidean Complex Algebra and Geometry of Higher Dimensions. It takes a vast wealth or knowledge of all fields of mathematics to apply all of the concepts in both Physics and Chemistry just to make a simple digital electronic switch... Just about everything I mentioned in this paragraph alone is needed if you were to design your own single transistor, never mind an integrated circuit. Then connect a billion of them together to make a CPU, another billion to make a GPU a few million to create your APU or Sound Card. This doesn't even account for Ram, PCI controllers(bridges) networking, interrupts for I/O devices such as mouse and keyboard... Then design the instruction set, convert that to an assembly language with an assembler, use the assembly language to create the C language, use that language to create the Operating System, Micro Controllers and device drivers. Run the operating system and create C++ either from C or Assembly or a combination of the two... Then use C/C++ to create APIs such as DirectX, OpenGL, Vulkan and other libraries and APIs. Then use all of those APIs to create Image and Video Editing Software, 3D Modeling and 3D Scene applications. Then use those applications to build some assets. Then start another project to create your Game Engine to incorporate those assets. Tie them all together into an integrated system. Now design the rules to your games, the levels, stages, the story, user interaction. You can not forget about the GUI part, even rendering or drawing text is no simple process. Now include all of the Physics Engine for doing motion, collision detection, A.I., path finding, scoring system, menus and item lists or inventory. Then integrate all of the sounds for sound effects and background music. None of this is any good if the scene looks terrible so you have to have good lighting so now right all of the shaders to do all of the lighting calculations for reflection, refraction, fog, how shiny or flat the surface looks. You need to calculate all of the normals coming off of the edges, faces and or vertices so that the lighting calculations are correct. This doesn't count for texture mapping... And so much more. So by the time you're done with all of that, you can then sit there and enjoy playing Tetris, Doom, Mario, Skyrim or Crysis...
Now when you go to the store and you spend $20 - $70 which may seem like a lot of money, just realize how cheap that is if you had to build your own computer from the transistors up and had to write all of those millions of lines of code. One syntax error and it fails to compile. Other errors and it can fail to link or build. Then it finally runs, until it crashes with an unexpected error, probably because you access an invalid memory address... Back to the debugging board... Ah fixed that crash, but the triangle doesn't look right... or it looks right until it spins then it gets all weird... Going back through the code and dropping in break points... Oh this should of been "+=" not "*=" or this should of been "0.001" not "0.01"... as these are run time errors...
I've been studying through vast tutorials only for years and I have followed and even made a 3D Game Engine from Scratch. No copying and pasting. I typed in everything manually as I followed along from either what I was reading or listening to. Hours of writing the code, configuring the build environment and many more hours debugging! But after creating that 3D Engine went on to use that Engine to build a 3D 1st Person Shooter style game and I can still run and play it to this day... No college education just the willingness to want to learn it and to apply it and the dedication to do it!
You can do anything you want if you put your mind to it!
skilz8098 I reread this a few times. I don’t know what to say but holy crap that’s insane!!! Thanks for taking the time to write it!
@@hullinstruments No problem at all. I am also a member of Stack Overflow and I try to help out others as much as I can with the knowledge that I have.
When I first started to learn C++ on my own, the internet was around but it was in its infancy so to speak. This was the transitional era from when it went from Dial Up to DSL-Cable. I graduated High School in 1999 and I didn't start learning C++ until about 2003.
Information at that time was there but it was limited and hard to find, also the type of content was very limited too. Most of the tutorials then were all text based, very few images and almost no videos since the data transfer rate through Internet Service Providers was very limited and wasn't very affordable either.
Not only that but many of the tutorials that I came across never told you how to set up your environment, never told you how to configure your compiler nor told you which compiler they were using nor what flags. They never told you how to debug etc. They mainly gave you a code snippet for a single function and were expecting you to know how to do it.
I'm assuming this because most of those who wrote these tutorials in the beginning already had a degree in Computer Science or Computer Engineering and their articles were probably geared towards those who were in College that had some kind of background in it already. It appeared that they weren't targeted towards complete beginners without any knowledge.
There were many challenges in the beginning and a slight learning curve. But with dedication and the willingness to learn it and to achieve certain goals; I was able to apply myself to finish the tasks at hand.
Now when I look back at the resources that I had and the limited amount of help that was available to me, I don't mind helping others who are trying to or want to learn.
I will be straight up with them and tell them that it is very difficult and that there is much to learn and know, but I will also encourage them to try and stick with it as it can be done as long as they are willing to dedicate themselves to put in the time, energy and effort to accomplish such tasks.
It's almost like asking a basic construction person (one who builds houses or small buildings) to learn how to build a bridge then go and build it where that bridge has a very coherent, sturdy and durable design that will last for many years while building it at the most cost effective price.
someone: **makes comment**
random dude:
okay, lemme tell ya my life story
@@skilz8098 What do you work with? Would be a pity of its not related to the things you've taught yourself.
Spent nearly 10 years performing metal inspect and earlier layer inspects, I wish I would have had a video like this to help me try to discern the topography that I saw.
Where were you from 93 - 2013 when I was inspecting this stuff ....
You were inspecting things and they didn’t teach you what you were looking at?
@@TheXGamer969
Well .... when you're fabricating, and I was in the photo resist strip section, you're not looking for "WHAT" is being made you're looking for resist that didn't get taken off before you stick it into a diffusion tube, or an annealing furnace and contaminate 300 other wafers.
You looked for incomplete etches or over etches. If you were curious you might stick a lot on a scope BEFORE you strip it just to see where it was being implanted ... Other than that ... No you don't get taught what transistors look like ....
I have crazy respect for the people who do this on more complex things like CPUs. Such fine detail and so much area to cover.
It really isn't done by hand anymore.
Most of the time, completely off-the-shelf library blocks are just assembled together and copied a massive number of times.
Then you would have input your design constraints and simulate the layout to ensure that all of the timing requirements are being met.
@@mortlet5180 that was then,valve too risk 'met hod'pixel brick trips[voltagz?]!encmaze
@@steveclem7873what
It's amazing how tiny is this technology and has begun to be used a very long time ago!
Isso que chamo verdadeiramente de Engenharia Reversa. Um mundo a ser explorado...
I have used a quad NAND chip before for a frequency to voltage converter.
It is cool to glimpse how one of them might be designed.
yuh, write
I love CMOS technology! Great for battery powered widgets. Has any one heard of or used RCA's 1802 CPU, a 40 pin DIP? Liked tinkering with that one a lot!
Yes! bought the ELF kit at a computer show in the late '70s. Interfaced it to an A to D converter.
The instruction set on that thing is a complete nightmare but it's an absolutely fascinating piece of electronics history.
@@EvilSandwich I'm curious, what makes a "good" vs "bad" instruction set on a small 8 bit processor?
Been watching a lot of louis rossman lately and the algorithm brings me this Lol
same here
what they have there is a transistor array that lends itself to creation of many different logic functions just by changing the interconnecting metal layer. Searching for B Series CMOS leads to a TI page describing the typical construction of inputs
thank you for taking so much effort and making it available to everyone.
i really appreciate it!
I would imagine there's a diode to VCC and a diode to GND to protect both over- and under-voltage conditions... That's probably what the second weird silicon thing is
That tan leg next to the pad is indeed a current limiting resistor, probably on the order of 100-200Ω. Next is most likely a zener connected to VCC, protecting the gate CMOS from inputs higher than VCC. Finally, the structure with GND on the inside loop and VCC on the outer. I suspect that's just a zener protecting the gate CMOS from inputs less than GND, but I'm not sure why it's surrounded by VCC. If you look directly above the NMOS unit you labeled Q1, you'll see there's a solid VCC structure there too. Do NMOS structures (where Source is grounded) need VDD (aka VCC) right outside their channel area to deplete it of electrons?
Robert - You're a 'special' breed of person to have produced this video.
In case you're still wondering, that is a COMPLIMENT!!!
I have a book suggestion for you - this is one that for some reason the NY Times Review of Books missed. Title: Conquering the Electron: The Geniuses...etc. Derek Cheung of Rockwell Scientific, MS/PhD EE Stanford is I think the main author. Particularly interesting are the later chapters that cover the development of the integrated circuit - he does a tremendously thorough and engaging summary of how we got to where we are today rustling these electrons. I have the audiobook and actually that is the version I'd suggest.
38:00 those weird things by the inputs are two diodes each, reverse biased from ground to the signal to VCC.
Negative voltages are shunted to GND. Positive voltages are shunted to VCC.
Static protection typically has a few Ohms resistance, diode to Vdd and diode from Vss, resistance, and diode to Vdd and diode from Vss.
Hi the quick explanation of what Q7/Q8 is with its "floatin" connection is something different.. This is how you create an AND gate in CMOS. @30:33 you can see Q7 from GND (blue) going to what you put in as Q8 (green) that is connecting to n1 (output of the transistor).In between you think you do have floating n4... however what it really is, that you have a single transistor with two gates. Both most be active to conduct GND to Out. So this is both nmos, that means, both inputs (n2 AND n3) must be active to let current pass from GND of Q7 to N1.. So it is actually not two transistors, but a single transistor with two gates and both need to be on to activate the transistor.
That is something you can see pretty often on cmos and a very simple way to AND stuff. So as you have dawn out, essentially it is 4 transistors. two of them ORed and two of them ANDed. Due to CMOS they need to have the same complementary setup...
Not sure if my explanation was good to understand, but in essence - the current needs to patth both pink gates (N2 and N3) to connect N1 to GND. Also I think it could have been done simpler in the diagram but as the circuit need to support a certain current, a single line Q was not enough, so they needed to double it up in lines.
the diode is for the antenna effect which would destroy the gate of mos while manufacturing
I thought the thumbnail was a GBC pokemon map at first
What are all of those 'bumps' on the metallization pads and traces?
I've seen them on other people's die shots as well, and everyone just says that it is dust or contamination from the decapping procedure; but, here I can clearly see that it is only present on the metallized traces...
Does anyone have any idea what those 'bumps'/'pits' actually are?
Contacts on the top metal layer that have most likely been etched exposed
I really like these informative hyper technical videos but i can't stop myself from laughing because you sound exactly like that boss guy from the movie Office Space lmfao.
Yah.. so if you come in on the weekend and reverse engineer some silicon for me.. that'd be great.
i suspect that ground/vcc ring is like a sheilding thing
You got it wrong your pin 1 (VCC ) is actually pin 7 (GND) simply by the fact that it connects outside the chip on the isolated metallic square around it best choice for a ground and that your pin 7 (which is pin 1) connects inside the chip good idea if you want to give power to the innards of a chip :P
This video just popped into my recommendation totally randomly
ic u ar en ver matrix java?
At the beginning you identified some pins saying they were a different shape they all look identical to me? lol
me too :( i dont even see any difference
It has its corners cut off
Now do an 8086 :D (kidding, please don't; we don't want you committed to an insane asylum as a result).
You could try doing something fun like another 74x13 (CMOS 4093) which is the same thing but with schmitt-triggers, or 74x14 (CMOS 4106) which is a hex inverter with schmitt-triggers. I think wither of those would be fascinating.
Thank you.
hello sir, I want to ask about the design of chips, graphic cards and other computer devices such as Intel, Arm Bionic chips, Apple, AMD, Nvidia. What software did they use to make it?
Wonderful information by wonderful personalty.
Has anyone used OpenCV to automap the polygons of each layer? Generating a netlist and masks from a decapped chip would be pretty darn cool
Great video! Those two inverters form an output buffer, otherwise fanout would be a problem after a couple of gates. Is this a HC version?
You can see 54HC00 in the silicon at the start, so yes it's high speed CMOS.
0:46 not pin but the pad has different shape
Great explanation and edit quality! Thank you for sharing this!! You earned my subscription!!
where is Pin 1 different from other pins? I really can not find any difference between Pin1 and any other pins
Pin one has its corners cut off.
@@RobertBaruch Thanks a lot. The author replied to me, it's really a exciting thing.
I'm a newbie about the chip and hardware things, I wonder if the video could be more detailed, for example, I guess the picture is a x-ray picture, and the white things in the chip is metal, but I don't know whether the chip has multiule layer, how you know two area are connected, it seems really obvious for you, however, it confuses me.
I think if you add those information in the next video, it will attract more people like me, and I think you and this video helps me a lot. As you audiance I really appreciate your work, thanks.
@@赶路人-q1w This was an optical microscope image. There is not much useful colour on Silicon ICs so the images are often black and white at the best available resolution.
Search for IC photomicrograph on the net or UA-cam and you will get lots of examples to study.
What magnification do you need to get to thisresolution?
Is this a regular photograph ? (as opposed to scanning electronic microscopy)
If so, how come everything seems so transparent ? Should there not be metallic tracks that ought to be opaque ?
It might be an x-ray picture
It's a normal photograph through a microscope. The white areas are the top metal layer. You can't see through it but it's probably not completely flat so you can see shadows where it goes over other features. The gray areas are probably silicon oxide which is transparent
@@max_kl Thank you.
I'm missing too much background. Does anyone know what the order of the layers is? Also, I can't figure out where the n/p regions are
what is the purpose of two inverters at the end ? isn't it equivqalent to no inverter at all ?
Most likely a buffer, something that doesn't change the logic value of the signal, but allows the receiver to draw more current from the output, and it also makes the edges sharper by amplifying the signal.
Is it possible to measure the area occupied by the capacitors, resistors, PMOS and NMOS transistors in microns?
que programa usaste
Why is the output transistor to Vcc so much larger than the one to GND? Because it's expected to drive loads?
IIRC, PMOS performance sucks compared to NMOS performance; so a large PMOS has comparable drive ability compared to a smaller NMOS. In fact, if you read the datasheet; the smaller NMOS can pull down harder than the huge PMOS! (NMOS has 0.4V drop while sinking 4mA, while PMOS has a 0.8V while sourcing the same.) And if you're thinking "aren't NMOS and PMOS just mirror images, shouldn't they have symmetrical performance?" -- No, the channel in one is N-type silicon and the other is P-type silicon. Different dopants, different majority carriers, different properties.
Mobility for the NMOS is usually 3 times higher than mobility for PMOS. That's why PMOS are 3 times bigger than NMOS.
Right, now that you say it, I realize I knew that. :)
Why'd you choose the blurriest quadrant?
Did I? I don't even notice anymore. The blurriness is unavoidable with DIY optics, so I kinda got used to it.
very informative reverse engineering thanks,waiting for another video.
Cool stuff. Is it possible to reverse engineer a modern processor? I feel that only automatization could handle the task that complex
Yes it is, but you will need a very good Scanning electron microscope and a team of engineers. We do it at our lab here in Texas and just one portion of a 22 nm processor took 8 months.
@@billjames1953 Good job. Texians are awesome. So, you could see if the Chinese put something queer in a chip? So, electron microscope could read internals? And no light limitations, i guess?
@@nailsaggitarius4212 we reverse engineer chips for either legacy parts that need to be re-made or for patent cases. But if we were asked to look to see if something was added, we could do that, but would need to see the original design.
@@nailsaggitarius4212 nut now jon,god a nueme ota...
Why do those transistors "meander" like that in a comb-like fashion? Is there any reason behind not using a bigger, simple-shaped area instead?
There are other shapes as well. It all depends on what you are trying to achieve. I have seen a circle with a bunch of finger overlapping it for a multi transistor. I think that was on an early microprocessor.
@@excitedbox5705 Yes, I'm aware that there are different shapes. What I'd like to know is - WHY? How does the shape influence the working of the transistor?
@@bonbonpony My guess is sonething about the capacitances, or about semiconductor's resistance. Doing it in a comb like pattern reduces it, shortening the paths
@@mzflighter6905 If it were about capacitance, combing would _increase it_ if anything, because this means more surface area between the electrodes.
But you might be onto something: this comb pattern might increase the length of the gate area between the two other electrodes, meaning "wider doorway" for more charge to flow through (higher currents), but without increasing the overall space the transistor takes on the silicon plate.
@@bonbonpony It is done that way to increase the effective gate width of the MOS transistor, which increases the drive current it can source or sink. It's the equivalent of having one very long finger, but since that's inconvenient, they fold it to make it have a more convenient aspect ratio.
do intel i9 9900k next
i believe in you
Yes. That is only a few billion transistors. So nothing special.
@@SkrovnoCZ babel rings 999 tho?..lawnden brigs iz foo ling 2own...
Richard Dreyfuss knows about IC’s?
grey matrixaz
...so I have a blown board which is 3 separate boards that come in a kit, how easy is it to trace power over a board? I get lost once it goes into a chip. Not that we do that stuff, but I’d like to be able to prove the point faster.
Depends on the board. Get a multimeter and it makes the job much easier. I recommend the Aneng Q1 or 8006. They are great starter meters and cost under $30.
@@excitedbox5705 hahaaa yuh write groooondes voltaz strait2blowit off of 000 noks yuh...
Yeah that's really SiMpLe
Anyway thanks for good content
could anyone explain why would we even want to connect double inverters?
I can't find reason other than adding delay which is usually avoided.
Sorry if its an obvious thing I'm still learning this stuff.
Probably they wanted to add a buffer acting like a Schmidt trigger, to avoid undefined states
Notice the SIZE of Q1 and Q2 (fairly big) and compare them to the SIZE of the preceding inverter (Q3 / Q4)...
The Q1/Q2 pair can handle WAY bigger loads (such as you might expect on the OUTPUT of the nand gate).
If you were to eliminate the Q3 / Q4 inverter altogether, you'd end up with.... an AND gate.
intel delay[as intels exsistsa?],blue traces[pre bluelightening ps2 escapades/mac/motorolla?]
See my explanation above... The output driver transistors are very large... driving them directly from the small logic transistors would slow the circuit down because of the large gate capacitance. So you have an intermediate inverter that has less gate capacitance than the output driver, but can provide a lot more current than the logic transistors. I've even seen cases with more than two inverters in a row, with each inverter being larger than the previous. (And you need an even number to keep it as a NAND gate rather than an AND gate.)
What is the purpose of the double inverter output?
The output driver transistors are very large... driving them directly from the small logic transistors would slow the circuit down because of the large gate capacitance. So you have an intermediate inverter that has less gate capacitance than the output driver, but can provide a lot more current than the logic transistors. I've even seen cases with more than two inverters in a row, with each inverter being larger than the previous.
Very instructional video. Thanks you very much :)
What is diffusion, and why is it floating?
I believe diffusion are the doped areas
What tools/softwares did you use?
For this video it sais it on the left top of the screen. Inkscape
What software are you.using?
collossus mach ivmxmilln?
Inkscape
@@max_kl thank you
Defs practiced this before recording :)
its an ol recycled repeat too...
youtube why the f.. did you bring me here? haha
This was great! Thanks
Quite interesting, thanks.
why there is no Capacitors on silicone dies ?
Because you can decouple it externally?
There ARE capacitors on silicon!!! A prime example being something like DRAM that has literally BILLIONS of caps.
In comparison, this exceedingly 'basic' nand gate doesn't WANT any on chip capacitors. It simply acts like a switch that connects the output pin to either VCC or GND depending upon the state of the two input pins.
As MZ flighter mentions, it is very common to place a (small-ish) external capacitor VERY near to and across the power supply pins for decoupling. Such decoupling capacitors act as tiny LOCAL power supplies when the output changes state. (Without decoupling caps, the potentially LONG and winding PCB traces to the power pins can act like inductors that can significantly s-l-o-w down the output switching so it's considered 'good practice [TM]' to include one for each 74xx chip if the board is to achieve the highest possible speeds.
Something else to keep in mind is that microchips are comparatively small (by definition). In order to make a capacitor of a 'meaningful' capacitance on silicon would consume a LOT of silicon real estate.
IIRC, in the late '60s, Fairchild polled some of their 'bigger' customers asking if they would pay a 'premium' for 74xx chips with 'built in' 0.1uF decoupling caps. Given what has survived today, I assume you can guess what he response was?
Footnote: You should take a look at the bottom of a PCB underneath a typical modern / powerful FPGA. It's like a small FOREST of decoupling caps for the various supply rails these things use.
@@trevorvanbremen4718 san francisco! [motorol/mac/60s apple reprise!]cap0jax
If you look at photomicrographs of switched capacitor filters in ICs (like modem of DTMF chips) you will find capacitors. They are low value so cost a lot of silicon real estate, they are avoided if possible and placed outside.
NAND chip already made up of NANDs: "What if we threw in two inverters just to get funky?'
Why is the layout of a single transistor so complicated? I always thought of a transistor as three blocks of alternatingly doped silicon put together. As far as I understand the green and blue regions at 10:41 are the collector and emitter (or the other way around) of the transistor and the pink/magenta region is the base. Why though are they arranged in this complicated intertwining layout and not, as taught on literally every website explaining transistors, as three blocks next to each other? Three blocks are probably easier to "print" onto the chips than this intertwining pattern, so there has to be a reason for this pattern.
What would those intertwined layers look like from the side? 3 blocks next to each other ;)
@@excitedbox5705 Yes, of course, but why this intertwining pattern? Seeing how microchips are produced I understand why it is easier to stack layers of silicon on top of each other than next to each other. But why don't manufacturers simply put literally three blocks of doped silicon on top of each other? Why is there this complicated intertwining pattern? Maybe this has something to do with capacitance or resistance?
These are called multi-finger transistors, IIRC their main purpose is to efficiently reduce the physical size of the layout compared with single-finger transistors. Also, depending on the circuit, it can also reduce gate resistances and improve device matching (you can split those transistors into several fingers and put them in a manner to fully utilise the floorplan while still retaining their W/L ratio)
@@sbtjlhw111 Thanks for your great answer, I've definitely got some reading to do now :)
And the term "multi-finger" kinda suggests that this "single" transistor (as I have thought about it) really is multiple transistors in parallel, which is kind of obvious now and I wonder how I didn't see that myself :D
The earliest transistors (we're talking way back in the 40s / 50s here) were exactly what you've stated. Three 'blobs'. However, these were Bipolar Junction Transistors (BJTs) rather than the Field Effect Transistors (FETs) that they were HOPING to produce.
With BJTs, it's far more difficult to just parallel a bunch together. (It CAN be done and is not uncommon in things like audio power amplifiers, but due to the minute differences between each BJT, it generally requires use of emitter resistors).
With MOSFETs on digital chips (where ALL of the devices are implicitly VERY close to each other in temperature etc), it's far more practical to directly parallel them without risking the thermal runaway issues you'd encounter with discrete BJTs
BTW, transistors on chips can often get 'weird'. It's not uncommon to see single devices that have MULTIPLE gates etc
I wonder if it's possible to reverse engineer c64 Vic and Sid chips, zx speccy ULA chip or Amiga AGA chip....
well they did the 6502 cpu, so it definitely should be possible
ua-cam.com/video/fWqBmmPQP40/v-deo.html
A lot of ULA chips were "Uncommitted Logic Arrays" that were connected up according to the customer design using the top metal layer so delivery times were reasonable and test masks could be used to characterise the chip. If you had access to the type of ULA core type and the mask design information you could reverse engineer it just by examining the top metal layer. However none of this information was ever made public and many of the companies no longer exist and the workers have retired it is hard to get official data. So one has to resort to transistor level.
With the ZX Spectrum you have a lot of enthusiasts who have worked on the designs for years. There may be a ULA design already out there. With the ZX 81 the ULA is very similar to all the logic chips in the ZX 80 that are now missing as the machines are almost the same with the exception of FAST mode. The Spectrum ULA will also share a lot of similar logic to the ZX8x with colour video managed fully in hardware instead of by the Z80 CPU as in the ZX8x.
What are those random dots?
english lingo
What is the app's name pls?
So, on the bottom left corner, we have the green circuit producing, the rocket fuel on the right side of the ... Oh wait sorry wrong video !
Quite involved.
walk the dawg,mojo?
Nice video, thank you!
Would this be possible for emulation? Could the schematics be flawlessly copied via microscope to make an emulator?
@Damion Manuel When I ask if emulation would be possible by reversing schematics, I'm talking about something LESS advanced than the NES. Like a tamagotchi or something.
@Damion Manuel Definitely something I'd want to get into. Archival such as emulation is one of my major interests.
@Damion Manuel 4lo ver yel0 brix rode0/soup/pear/mario?...
@Damion Manuel not look en faa in awf?..t&ceasers...glint
damn cuh luvya cuh
please the name of this drawing software please ?
inkscape
Немного сумбурно по узлы n1..n7, я ещё раз посмотрю.
Gods among Men.....
please , reverse engineer "Kr580vm80a" intel 8080 (compatible)
yuh muva caine tru georgia,coom ring yellz2san foo sys kohl beige...?
Next step, reverse engineer a modern cpu from electron microscope images
Many years ago, I worked at a company that did just that. Of course, it was utterly impractical to reverse-engineer a complete CPU, but you could do bits and pieces such as PLLs and other interesting circuits. The technology to reverse-engineer modern ICs is quite incredible.
>>Simple
We know that nand gate have just two transistors,why there a lot of transistors?😂
I always see a lot of 2 dimensional organization... Wonder why the depth has never been truly utilized... Granted this is probably why the newer quantum is layered stacks yet theirs so much space that's not being utilized. Would be an interesting path and routing if a 3D printer is developed to create newer design.
Designers minimize layers because it greatly reduces cost. Also think more layers would also mean it takes longer and would increase manufacturing errors. Sometimes simpler is better!
High-density DRAM chips use capacitors etched into a trench in the silicon, so they do somewhat make use of the depth.
Can you reverse engineer the chips on the XboxOne so I can mod my system already???
shuddup ye filtea spykey,sovx,yuh
I think your power n ground are reversed, just what I think cool vid
reversed as yoo wrote,sung,said,onlined it..enc spam kipper cores,term
Metal semiconductors what about plastic. Ten power 23.
en plain english please,suburu?
Would it be possible to reverse TI BQ2040 BMS chip to read firmware from its ROM?
The specification is wrong regarding smbus write through function to external EEPROM and it would be interesting to check what is happening.
From the datasheet for that chip, the whole contents of ROM are listed in a table. Maybe it's more useful to have a logic analyzer to check the data and address bus for EEPROM communications.
@@mateijordache1952 The idea is to directly access external EEPROM through smbus without need to dissasemble or direct soldering to eeprom. The function is there but doesn't work as in datasheet so there are something that is not documented. For BQ2060 it works correctly.
wrong=rung[synchro/compares/synthesis/2unes bi folk corls!..]voliz...
@@mateijordache1952 morsils pol?
👍
懐かしい。
maybe soon we can use deep learning AI to reverse engineer this stuff :}
Look at data, label by color and name, repeat
pixel rubrics,bees,col en eees?
So much work - but what for?
Isn't learning cool stuff enough a reason? :q
ar u alezbiang?
so idiotic chip 4 bit not-and gates. this layout cant be used to make a 8/16bit variations
yuh not a very angroon violent main spammer aryu?
Love the video, but Jesus Christ can you mute the audio when you’re speeding through parts? Sometimes you do, and sometimes it’s not even that bad. But especially towards the beginning the loud squeaks are super unpleasant. Like I’m not trying to be petty, but it was a serious problem for me.
It was pretty bad, wasn't it? Definitely muting the audio next time.
I’m glad I stuck through it though, it was really only the first bit and since then I’ve watched probably about another 6 hours of content on your channel. It’s a little above my head but I’m really enjoying it, keep up the good work man.
jc crux look out rsj said girdaz=personal[personality ciezures readline a1?]v2 waystarz,enc0[wtf sence iz a?]
Thanks for sharing!