Kindly make one video for chiplet technology Introduction to chiplet technology: what is it, how does it work, and what are its benefits? Different types of chiplets: compute, memory, I/O, and so on The challenges of chiplet technology: designing, manufacturing, and packaging chiplets The future of chiplet technology: how it is expected to impact the semiconductor industry
Very good suggestions but I am afraid I don't have time to make video now. Let me try to answer for your questions in here before full video at some time later. I hope it can help even little bit. 1. What is chiplet? - Chiplet is to split one big SoC(System on Chip) into multiple smaller chips. 2. How does it works? - In one big SoC there are multiple sections for different functions such as compute, memory, I/O etc. and chiplet separates these functions as individual chips. Each chip of chiplet should have some level of duplicated functions to communicate each other which is not necessary in SoC. It means total chip area of chiplets is larger than SoC. Each dies of chiplet can be connected by using Si interposer, RDL interposer or package substrate. 3. Benefits of chiplet - Each function in one SoC has optimum Si node e.g. 5nm, 45nm, 65nm etc. and cost of smaller node is much higher than larger node. But SoC can't use different optimum nodes for many functions because it is single chip. Even if there is small defect for only one function, whole SoC is reject and it means manufacturing yield is relatively lower than chiplet. Chiplet is multiple chips so chiplet can use optimum Si node for each function. If there is small defect for one chip, only that chip is reject and other chips are still good. So manufacturing yield of chiplet is relatively higher than SoC. Development time of chiplet is shorter than SoC because SoC is much more complex than chiplet and chiplet can develop multiple chips in parallel separately. 4. Different type of chiplet - As you said, compute, SRAM memory, I/O, FPGA, SerDes etc. 5. Chiplet Package Technology - 2.5D using silicon interposer, 2.3D using RDL interposer, 3D using hybrid bonding 6. Impact on semiconductor industry - Chiplet is already widely used technology and it reduces development time and cost of new semiconductor chip and sometimes improve performance as well.
In 2.5D package, logic die and HBM memory module are located on Si interposer side by side and electrically connected through Si interposer. And this Si interposer has TSV. In 3D package, memory die typically SRAM is stacked on logic die vertically and logic has TSV. It does not have Si interposer. 2.5D has TSV in Si interposer but 3D has TSV in logic die. 2.5D has logic die and HBM memory module side by side but 3D has memory die is stacked on logic die vertically.
My name is Nishanth, and I am a student at the Indian Institute of Technology Hyderabad. I am asking a question about packaging architecture. I am currently working on a project that requires me to research different types of packaging architecture. I wasn't able to find the packaging architecture in online. kindly give some suggestions sir
I don't know well about protocol and here are what I heard. Communication protocol for chiplet is UCie(Universal Chiplet Interconnect Express). Please check their website and UA-cam channel. www.uciexpress.org/#:~:text=%E2%80%8B,interoperable%2C%20multi%2Dvendor%20ecosystem. www.youtube.com/@ucieconsortium/videos Communication protocols for board level are I2C, I3C, and SPI. en.wikipedia.org/wiki/I%C2%B2C en.wikipedia.org/wiki/I3C_(bus) en.wikipedia.org/wiki/Serial_Peripheral_Interface
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thank you very much for your thorough explanation.
Excellent explanation thank you!
great video as always !! finally I get the difference between 2d, 3d and 2.5d
great video! thanks for the work!
Very easy to understand, well done!
Kindly make one video for chiplet technology
Introduction to chiplet technology: what is it, how does it work, and what are its benefits?
Different types of chiplets: compute, memory, I/O, and so on
The challenges of chiplet technology: designing, manufacturing, and packaging chiplets
The future of chiplet technology: how it is expected to impact the semiconductor industry
Very good suggestions but I am afraid I don't have time to make video now.
Let me try to answer for your questions in here before full video at some time later. I hope it can help even little bit.
1. What is chiplet?
- Chiplet is to split one big SoC(System on Chip) into multiple smaller chips.
2. How does it works?
- In one big SoC there are multiple sections for different functions such as compute, memory, I/O etc. and chiplet separates these functions as individual chips. Each chip of chiplet should have some level of duplicated functions to communicate each other which is not necessary in SoC. It means total chip area of chiplets is larger than SoC. Each dies of chiplet can be connected by using Si interposer, RDL interposer or package substrate.
3. Benefits of chiplet
- Each function in one SoC has optimum Si node e.g. 5nm, 45nm, 65nm etc. and cost of smaller node is much higher than larger node. But SoC can't use different optimum nodes for many functions because it is single chip. Even if there is small defect for only one function, whole SoC is reject and it means manufacturing yield is relatively lower than chiplet.
Chiplet is multiple chips so chiplet can use optimum Si node for each function. If there is small defect for one chip, only that chip is reject and other chips are still good. So manufacturing yield of chiplet is relatively higher than SoC. Development time of chiplet is shorter than SoC because SoC is much more complex than chiplet and chiplet can develop multiple chips in parallel separately.
4. Different type of chiplet
- As you said, compute, SRAM memory, I/O, FPGA, SerDes etc.
5. Chiplet Package Technology
- 2.5D using silicon interposer, 2.3D using RDL interposer, 3D using hybrid bonding
6. Impact on semiconductor industry
- Chiplet is already widely used technology and it reduces development time and cost of new semiconductor chip and sometimes improve performance as well.
Your video is the best!
Thank you very much for the informative and clear explanations.
Thank you for sharing !!!
이해하는데큰 도움이되네요.
awesome video
Thanks
Thanks for sharing, your material is worth for studying. And I have a question for you that it should be 3D PKG image at 4:30 not 2.5D right?
Thanks for watching! It is 2.5D package at 4:30 because it uses Si interposer.
@@semicontalk3223 but it is stacked with DRAM and Logic as image through TSV solution ? :)
In 2.5D package, logic die and HBM memory module are located on Si interposer side by side and electrically connected through Si interposer. And this Si interposer has TSV.
In 3D package, memory die typically SRAM is stacked on logic die vertically and logic has TSV. It does not have Si interposer.
2.5D has TSV in Si interposer but 3D has TSV in logic die. 2.5D has logic die and HBM memory module side by side but 3D has memory die is stacked on logic die vertically.
이 아저씨 지적수준이 엄첟 높습니다
My name is Nishanth, and I am a student at the Indian Institute of Technology Hyderabad. I am asking a question about packaging architecture.
I am currently working on a project that requires me to research different types of packaging architecture. I wasn't able to find the packaging architecture in online. kindly give some suggestions sir
Thanks for asking. Please check below material.
ewh.ieee.org/soc/cpmt/presentations/eps2204c.pdf
hello, sir what is the type of communication protocol used by Chiplet and board level why?
I don't know well about protocol and here are what I heard.
Communication protocol for chiplet is UCie(Universal Chiplet Interconnect Express).
Please check their website and UA-cam channel.
www.uciexpress.org/#:~:text=%E2%80%8B,interoperable%2C%20multi%2Dvendor%20ecosystem.
www.youtube.com/@ucieconsortium/videos
Communication protocols for board level are I2C, I3C, and SPI.
en.wikipedia.org/wiki/I%C2%B2C
en.wikipedia.org/wiki/I3C_(bus)
en.wikipedia.org/wiki/Serial_Peripheral_Interface
2.5D~
Is interposer always be Si or there any others?
Interposer can be Si, glass, and RDL layer of fan out technology. But currently almost of all interposers in the market is Si.
What is the difference between this presentation's 2.5D and recent Samsung 3.5D?
I don't know what Samsung 3.5D. Would you let me know where you heard about Samsung 3.5D?
@@semicontalk3223 Samsung Market Strategy SVP presents Advanced Heterogeneous Integration new 3.5D in Samsung Foundry Forum 2021 on Oct/6 - Oct/8.
I see. Samsung said that 3.5D is a combination of 2.5D and 3D but there is no more information. So their 3.5D will be little bit different than 2.5D.
I thought you are Indian, but I check out your profile fink you are from Korea wow