Xilinx FPGA-HDMI1.4: You Must Know First !

This in-depth design is what you should go first to be able to work with Industry-Standard FPGA HDMI designs.
#This gives you #complete #in-depth #information that #how the FPGA HDMI works. This will eventually cover #Zedboard, #KC705, #SP701, #AC701, #ZC706, #ZC702, and #VC707 FPGA board HDMI #circuitry information, #Vivado #pipeline #design, #SDK #application writing, and running the design on the #board.
#Xilinx #FPGA-#HDMI1.4: #You #Must #Know #First !
Complete In-depth Design Article with Source Code, IP, and Board References Links:
Will be Updated
Complete Step-by-Step Design & Demonstration:
• ZedBoard HDMI1.4 Worki...
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Chapters
--------------------------------
00:06 - Intro
00:36 - Xilinx Boards to Cover
01:30 - HDMI1.4 TX IC In Xilinx FPGA Boards
02:14 - AVD7511 HDMI TX IC
02:36 - AVD7511 HDMI TX IC with Separate Sync and Embedded Sync
03:14 - HDMI Input Formats supported by ADV7511 HDMI TX IC
03:30 - HDMI Configuration in ZedBoard, KC705 & ZC702
04:10 - HDMI TX Circuit Schematics of ZedBoard, KC705 & ZC702
05:00 - HDMI Configuration in ZC706, AC701 & SP701
05:20 - HDMI TX Circuit Schematics of ZC706, AC701 & SP701
05:40 - HDMI Configuration in VC707
05:56 - HDMI TX Circuit Schematics of VC707
06:05 - Vivado Hardware Block Design
09:27 - Constraint Mapping
10:34 - Constraint Mapping - I2C Bus on FPGA Boards
11:00 - Coding - Vitis SDK Application
11:36 - Coding - I2C Configuration
11:57 - Coding - Register Programming
13:40 - Building and Running Design
13:49 - Output
14:16 - Conclusion

[@trevorcrowley5748]

What you are doing is very difficult and extremely helpful. Most of the similar content out there for Zynq / HDMI / ADI is opaque, from 2018, and deprecated. Subscribed

[@tiatanten]

I enjoyed your video with learning. Thanks! I really like this channel now.

[@nielfotech4684]

This means a lot for us. Keeping supporting this channel. More similar videos are coming.

[@karthickjgk7783]

Good work. 🎉

[@TahaAlars]

amazing, thank you

[@RixtronixLAB]

Cool video shot, keep it up, thank you for sharing :)

[@nikolaykostishen6402]

Thanks! Very nice tutorial.

[@nielfotech4684]

Thanks! Keep following this channel.

[@jajajaj666]

Hi, good video.
In the case of the ZedBoard, an HDMI output IP is provided by Avnet, what is the purpose or these IPs? if we can constraint the output from the AXI Stream to video Out?
Thanks man

[@nielfotech4684]

Thanks for the comment.
Yes, there is also Avnet IP for the ZedBoard HDMI Output interface. The IP is not doing the biggest thing there. Apart from parallel video interfacing, the IP is adding an extra Xilinx FPGA primitives to relate between the clock and data thing, which is not critical at this moment. So that, we can also avoid this IP and directly do the constraint mapping from Axi4-stream-to-video-out IP to IC. So, for this case, using IP or not using IP will not be going to severely affect the design output.
However, the constraint mapping from Axi4-stream-to-video-out IP to IC totally depends on the HDMI TX IC circuity as mentioned here 02:36. If it has separate sync pins (xilinx boards' hdmi tx ICs are mostly configured with separate sync configuration. ZedBoard also has this configuration), then we can directly do the constraint mapping otherwise, in the case of embedded sync configuration, we will need custom logic or IP to interface.
Thanks!

[@allenzheng6553]

Good video, Thanks.
Is the source code for the Zedboard posted anywhere?

[@saadtiwana]

Very nice and informative video. Do you know of any reference design that decodes video received with embedded syncs? BT.656 or BT.1120

[@HowardGraves-i2s]

Is the source code and example project for the Zedboard posted anywhere?

[@nielfotech4684]

Thanks for your interest. Keep checking the description of this video, I will soon publish a detailed design with source code.

[@colt6006]

😞 "Promo sm"

[@y_x2]

He talk too fast! I have design a core for HDMI.

[@nielfotech4684]

Great!