#2 -- RAM on DE2 and Cyclone

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  • Опубліковано 24 гру 2024

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  • @hayral
    @hayral 5 років тому +5

    32:45 "You can't do that in verilog!"
    then 33:15 dramatic zoom on "x h"

  • @dr.tahabasheer2753
    @dr.tahabasheer2753 9 років тому +2

    Hi, thank you for uploading , from where some one can get the lab files?

    • @ece4760
      @ece4760  9 років тому +1

      +Ph.D Student people.ece.cornell.edu/land/courses/ece5760/

    • @dr.tahabasheer2753
      @dr.tahabasheer2753 9 років тому

      +Bruce Land Thank you, I will test them , thanks again again for this great favor.

  • @NguyenHuuNamDuong
    @NguyenHuuNamDuong 9 років тому +1

    What's the textbook for this course?

    • @ece4760
      @ece4760  9 років тому +2

      +Nguyen Huu Nam Duong Rapid
      prototyping of Digital Systems -- SOPC edition
      by JO Hamblen, TS Hall and MD Furman.

  • @jaehyuklee908
    @jaehyuklee908 7 років тому

    Hi, very nice lectures. I really appreciate it. BTW Could I get the lab files for the 2012 lectures? I could only find the lab files for 2018 lectures. in the link you've provided.

    • @ece4760
      @ece4760  7 років тому +1

      people.ece.cornell.edu/land/courses/ece5760/LABS/oldlabs.html
      And
      people.ece.cornell.edu/land/courses/ece5760/index_old.html

    • @jaehyuklee908
      @jaehyuklee908 7 років тому

      Bruce Land I really appreciate all your help and teaching. Happy new year :)

    • @ece4760
      @ece4760  7 років тому

      Thanks

  • @chasep255
    @chasep255 9 років тому

    Why do you use blocking assignments in the case statement for the ROM example. Shouldn’t it be non-blocking since it is in a clocked always?

    • @ece4760
      @ece4760  9 років тому

      +Chase Preuninger Probably should be but I was following the Altera style manual page 12-27 in www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii5v1.pdf

    • @chasep255
      @chasep255 9 років тому

      +Bruce Land Ok, I have just never really seen blocking assignments used in clocked always blocks. I actually have a xilinx card so I will try to find out how they do it.

    • @niklaswallin9478
      @niklaswallin9478 8 років тому

      I imagine case will "isolate" it, you can even mix = and

  • @waiyan1497
    @waiyan1497 6 років тому

    Are the lecture slide files for these?

    • @ece4760
      @ece4760  6 років тому

      All lectures are based on web pages and notes. There are no "slides". The DE2 has been replaced by DE1-soC using cyclone5. You may want to refer to the newer lectures

  • @KLATUBARARA1
    @KLATUBARARA1 12 років тому

    Look for
    My First Nios II Tutorial (2)

  • @JulieanGalak
    @JulieanGalak 6 років тому

    Generating LUT code in Perl vs Matlab vs C. Last time I had to do that, I ended up using Excel... :)
    (this was for a C LUT for an AVR, not Verilog, but same idea)

  • @ahbushnell1
    @ahbushnell1 11 років тому

    Assign homework to clean erasures