Hi, very nice lectures. I really appreciate it. BTW Could I get the lab files for the 2012 lectures? I could only find the lab files for 2018 lectures. in the link you've provided.
+Chase Preuninger Probably should be but I was following the Altera style manual page 12-27 in www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii5v1.pdf
+Bruce Land Ok, I have just never really seen blocking assignments used in clocked always blocks. I actually have a xilinx card so I will try to find out how they do it.
All lectures are based on web pages and notes. There are no "slides". The DE2 has been replaced by DE1-soC using cyclone5. You may want to refer to the newer lectures
Generating LUT code in Perl vs Matlab vs C. Last time I had to do that, I ended up using Excel... :) (this was for a C LUT for an AVR, not Verilog, but same idea)
32:45 "You can't do that in verilog!"
then 33:15 dramatic zoom on "x h"
hahahahahah
Hi, thank you for uploading , from where some one can get the lab files?
+Ph.D Student people.ece.cornell.edu/land/courses/ece5760/
+Bruce Land Thank you, I will test them , thanks again again for this great favor.
What's the textbook for this course?
+Nguyen Huu Nam Duong Rapid
prototyping of Digital Systems -- SOPC edition
by JO Hamblen, TS Hall and MD Furman.
Hi, very nice lectures. I really appreciate it. BTW Could I get the lab files for the 2012 lectures? I could only find the lab files for 2018 lectures. in the link you've provided.
people.ece.cornell.edu/land/courses/ece5760/LABS/oldlabs.html
And
people.ece.cornell.edu/land/courses/ece5760/index_old.html
Bruce Land I really appreciate all your help and teaching. Happy new year :)
Thanks
Why do you use blocking assignments in the case statement for the ROM example. Shouldn’t it be non-blocking since it is in a clocked always?
+Chase Preuninger Probably should be but I was following the Altera style manual page 12-27 in www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii5v1.pdf
+Bruce Land Ok, I have just never really seen blocking assignments used in clocked always blocks. I actually have a xilinx card so I will try to find out how they do it.
I imagine case will "isolate" it, you can even mix = and
Are the lecture slide files for these?
All lectures are based on web pages and notes. There are no "slides". The DE2 has been replaced by DE1-soC using cyclone5. You may want to refer to the newer lectures
Look for
My First Nios II Tutorial (2)
Generating LUT code in Perl vs Matlab vs C. Last time I had to do that, I ended up using Excel... :)
(this was for a C LUT for an AVR, not Verilog, but same idea)
Assign homework to clean erasures