First Project With Lattice FPGA - Part 3: Verilog

[@freeelectron8261]

Good tut Dom! You explain everything and don't rush things - thanks!

[@Dom-bo8wd]

Im so so so glad you liked it! Thanks for the feedback :)

[@nguyenminh862003]

Can read data from it

[@smokerji9768]

tysm well explination

[@caleb7799]

cool, but what's with the lip smacking? lol