FPGA, in fact, is a low-cost practice of mapping algorithms to hardware, which is another perspective on algorithms. I am a developer of xilinx Vitis Library image Codec. Four years ago, I was not familiar with WebP algorithm when I used HLS. It took me four months to achieve the price efficiency and power consumption efficiency of CPU 3X, which is still surprising. In fact, RTL can be further improved by 3 to 10 times. The problem with FPGA is that the mapping of top-level branches to the area will inevitably lead to a decline in efficiency. You must let the branches sink, which is a great test for understanding the algorithm. Sometimes you even need to understand the essence of the algorithm more than the algorithm developers, because more and more algorithms tend to explore the problem space extensively and then select the best. What you can do is to find the one with higher probability among the branches, and give it the most resources, while the other branches use the least area. When you can discover this probability, you actually discover a new knowledge. Isn't that a gain?
One minor correction, Ben claims circuit minimization is NP-complete, but that's not true, it's not in NP at all and therefore not NP-complete. It's actually much worse than NP-hard, circuit minimization is Σ₂ᴾ-complete, the next level of the polynomial hierarchy, and is therefore (in some sense) vastly harder than anything in NP.
vendors: we introducing high level synthesis us: so we can use a higher level language and abstractions to build our systems vendors: yes, you can accelerate your design process us: so which kind of high level language. python, scala, ocaml... vendors: we're giving you the highest of high level languages....C us: ....srsly
@OLDSKOOL978 There is a large space of languages and features that allow for effectively writing composable HDL that doesn't involve hacking up some imperative language and calling it an improvement. The current HDL languages leave much to be desired, but C is not the answer.
It's not really "C" either, with all the crazy directives. The person who works on it pretty much has to know the nuts and bolts of RTL level of representation well. This implies a smaller user base that leads to harder to find support for anyone who works outside of professional design houses.
![FPGAs are (not) Good at Deep Learning [Invited]](/img/n.gif)
FPGA, in fact, is a low-cost practice of mapping algorithms to hardware, which is another perspective on algorithms. I am a developer of xilinx Vitis Library image Codec. Four years ago, I was not familiar with WebP algorithm when I used HLS. It took me four months to achieve the price efficiency and power consumption efficiency of CPU 3X, which is still surprising. In fact, RTL can be further improved by 3 to 10 times. The problem with FPGA is that the mapping of top-level branches to the area will inevitably lead to a decline in efficiency. You must let the branches sink, which is a great test for understanding the algorithm. Sometimes you even need to understand the essence of the algorithm more than the algorithm developers, because more and more algorithms tend to explore the problem space extensively and then select the best. What you can do is to find the one with higher probability among the branches, and give it the most resources, while the other branches use the least area. When you can discover this probability, you actually discover a new knowledge. Isn't that a gain?
I like soup.
I would love to hear the speaker's thoughts on what ended up happening on the GPU side and what a similar resolution would look like in FPGAs.
FPGAAAAA - that must be some kind of acronym world record (most contiguous A's in an acronym)
One minor correction, Ben claims circuit minimization is NP-complete, but that's not true, it's not in NP at all and therefore not NP-complete. It's actually much worse than NP-hard, circuit minimization is Σ₂ᴾ-complete, the next level of the polynomial hierarchy, and is therefore (in some sense) vastly harder than anything in NP.
There are full screen red flashes throughout the video.
Thks again
This isn't twitter.
vendors: we introducing high level synthesis
us: so we can use a higher level language and abstractions to build our systems
vendors: yes, you can accelerate your design process
us: so which kind of high level language. python, scala, ocaml...
vendors: we're giving you the highest of high level languages....C
us: ....srsly
So true.
@OLDSKOOL978 Except it's designed for a turning machine. It really is a failure to think of c as a "good" choice in any sense of the word for HDL.
@OLDSKOOL978 There is a large space of languages and features that allow for effectively writing composable HDL that doesn't involve hacking up some imperative language and calling it an improvement. The current HDL languages leave much to be desired, but C is not the answer.
@OLDSKOOL978 I completely agree. Exactly my thoughts.
It's not really "C" either, with all the crazy directives. The person who works on it pretty much has to know the nuts and bolts of RTL level of representation well. This implies a smaller user base that leads to harder to find support for anyone who works outside of professional design houses.