Full Adder Design In Xilinx Vivado.

[@anantk6222]

great sir i appreciate your efforts ,you are truly amazing

[@dr.hariprasadnaikbhattu]

Thanks for the appreciation

[@animal.lover3463]

Nice content sir
TQ for sharing your knowledge

[@dr.hariprasadnaikbhattu]

Thanks 👍

[@ChiragHadiya]

first class and un doubtable concept clear understanding

[@dr.hariprasadnaikbhattu]

Thank you so much 👍

[@kavyastrendingbeatz6874]

Super clear explanation sir

[@dr.hariprasadnaikbhattu]

Thanks for the appreciation

[@manjula-hq8ts]

Can we get 3 input gates like 3 input and , or gate?

[@dr.hariprasadnaikbhattu]

Hi, you can it depends on the Boolean expression

[@manjula-hq8ts]

@@dr.hariprasadnaikbhattu but how to take 3 inputs on vivado sir, for example pla uses limited and gates but taking 2 inputs it's shows many and gates in schematic

[@faizaman9267]

Sir please make a video of the installation of Xilinx on Windows 11

[@dr.hariprasadnaikbhattu]

Hi, There are many videos on youtube. Kindly go through it

[@GiStormy]

Thank you so much!

[@dr.hariprasadnaikbhattu]

You are Welcome

[@ravikantgang7396]

Sir,
verilog code in xilinx costume library how to make and use it

[@dr.hariprasadnaikbhattu]

Hi, use IP core the custom design
I have other videos go through them

[@thesailaja5941]

Thank you sir 😊

[@dr.hariprasadnaikbhattu]

Welcome

[@kolaveri70]

Thanks

[@dr.hariprasadnaikbhattu]

Thanks 👍

[@MKP_CreateOwnwork]

HA1 kya h

[@dr.hariprasadnaikbhattu]

Hi, HA1 and HA2 are instance NAMES used to build a full adder.

[@rahulbhattu7661]

Thanks

[@dr.hariprasadnaikbhattu]

Thanks