Synthesizable Matrix Multiplication in VHDL
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- Опубліковано 4 лис 2024
- The VHDL code is available from my Blog : vhdlguru.blogs...
The video simply explains the code and how it can possibly be converted for handling different sized matrices.
I have used Modelsim SE for testing the code.
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thank you for your code. I used it to learn
Thank you!
Can you please tell me whether this code can be used for Basys 3 FPGA?
it can be used. but not directly as inputs and outputs are 72 bits each. so you would need to write a wrapper to input numbers in multiple stages. and also show the output in multiple stages. like you set the switches, push a button and then change the switches and so on.
@@VCodes Can you provide me the code if possible?
I dont have the code readymade for this. but you can write up a state machine for this. if you attempt it, I can guide you through the process. but I do charge a fee for my time. send me an email if you want.
hello.
can you help me do this:
dedicated datapath capable of multiplication
prod = 0
INPUT A
INPUT B
WHILE ( B != 0 ) {
prod = prod + A
B = B - 1
}
OUTPUT prod
in behavioral VHDL?
Yes! There is a very similar code in this blog post: vhdlguru.blogspot.com/2010/03/how-to-do-clocked-for-loop.html
Hii sir how can i contact you
my email is available here: vhdlguru.blogspot.com/p/contact-me_23.html
Great!! Thanks :) but could one not do it simpler ? more like in C/C++ ? for that in C in need like 40 lines only.. without state machine
you can. but it will be hard to synthesis it.
@@VCodes When you do the multiplication of two elements, its 8-bit unsigned x 8 bit unsigned ->> this puts out a 16bit unsigned value. Why are you storing it in a 16 bit temp-variable and then cut off 8 bits when putting it into the output matrix? Arent you loosing information, when multiplying higher numbers?
To my first question, i wrote your matrix multiplication a little shorter, and although there are not really any matrices involved, it kinda does the same job, would you agree ? ;D
github.com/Wale94/matrix_multiplication_vhdl.git
@@dukenuke2690 if you are getting the correct results, and code doesnt need to be synthesisable, anything is fine. my code is simple and based on the assumption that the output matrix doesnt have numbers greater than 255. The code is done more for educative purposes which someone can play around with and learn more.
@@VCodes :) ah ok i get it. Why would my code not be synthesizeable ? number of IO Ports could be connected to some other Core or BRAM
@@dukenuke2690 Good. you have lot of questions. I can provide guidance for a fee. you can write to me at lalnitt (at) gmail (dot) com