What a gem! I really like your code review series, both xv6 and this one. The diagrams and flowcharts are clear and quite informative. Salute and love from China.
Really enjoyed this. It's been a *long* time since I did this sort of thing so it was a ton of fun going through it with you. It brings back lots of fond memories.
Thanks for this code walkthrough video. It's clear that the CPU shown is a single cycle family or even perhaps a multicycle, is this core for testing purposes ? is there an available pipelined core source code where we can see how the pipeline hazards are solved ? what about a CISC open source core, seems also exotic.
I have been looking through the actual RISC-V documentation and it seems you have a mistaken idea of what the JAL primary opcode is, which is 1101111 which for some reason you are saying it is 0111111
You are correct about the opcode for JAL. I’m not sure what part of the video you are referring to and I’m not planning to re-watch to locate it. But if I said otherwise, I must have misspoken. I strive to get all these details correct, but I’m amazed there are people like you, who are able to catch errors like this.
@@hhp3 The reason I didn't give a timestamp was because it seemed like every time it was mentioned you had a "corrected" version that was incorrect and that confused the heck out of me. Although a timestamp where it does happen that I was able to go back and find is 32:20.
@@christopheriman4921 I looked at the video at that point and I am completely wrong. Big time. Frankly, it’s embarrassing to find such blatant errors, especially when I’m criticizing someone else for their errors and it’s really my error. The mistake arose in my notes so I made this same mistake in another video as well. Anyway, thanks for correcting me.
@@hhp3 No problem, I can see how the error could have occurred very easily from the number that you ended up using. It seems like you had just looked at the wrong part of the opcode and jotted it down when checking stuff being quite literally off by 2 bits and because in RV32I the 2 least significant bits are always 11 you put 11 at the end.
Found another gold mine on the internet.. So grateful.. Keep up the good work. Love from Sri Lanka
What a gem! I really like your code review series, both xv6 and this one. The diagrams and flowcharts are clear and quite informative. Salute and love from China.
Glad it was helpful!
Really enjoyed this. It's been a *long* time since I did this sort of thing so it was a ton of fun going through it with you. It brings back lots of fond memories.
Thanks for this code walkthrough video. It's clear that the CPU shown is a single cycle family or even perhaps a multicycle, is this core for testing purposes ? is there an available pipelined core source code where we can see how the pipeline hazards are solved ? what about a CISC open source core, seems also exotic.
Great video!
Hi sir from.india,i really respect you as i learned quines from you
Glad to hear that
@@hhp3 its a privilege to have you response sir
I have been looking through the actual RISC-V documentation and it seems you have a mistaken idea of what the JAL primary opcode is, which is 1101111 which for some reason you are saying it is 0111111
You are correct about the opcode for JAL. I’m not sure what part of the video you are referring to and I’m not planning to re-watch to locate it. But if I said otherwise, I must have misspoken. I strive to get all these details correct, but I’m amazed there are people like you, who are able to catch errors like this.
@@hhp3 The reason I didn't give a timestamp was because it seemed like every time it was mentioned you had a "corrected" version that was incorrect and that confused the heck out of me. Although a timestamp where it does happen that I was able to go back and find is 32:20.
@@christopheriman4921 I looked at the video at that point and I am completely wrong. Big time. Frankly, it’s embarrassing to find such blatant errors, especially when I’m criticizing someone else for their errors and it’s really my error. The mistake arose in my notes so I made this same mistake in another video as well. Anyway, thanks for correcting me.
@@hhp3 No problem, I can see how the error could have occurred very easily from the number that you ended up using. It seems like you had just looked at the wrong part of the opcode and jotted it down when checking stuff being quite literally off by 2 bits and because in RV32I the 2 least significant bits are always 11 you put 11 at the end.
Awesome ! (but maybe I'm not 100% objective )
Thanks so much!!!
Hello Dear Professor . why don't you use BSV instead of Verilog for implementation ?
I think it should be SV instead of BSV. SV is more used