So, my guess is that when we do port mapping, it does not add delta delay. Am I right? I mean when we instantiate a component and do port map for that. Because if it's going to add delta delay, then when we port map the clock of a component to the clock of the top level (which is a quite common practice), then inside that component will not be in sync (from delta cycle clock point of view) with the top level anymore.
Or it could be that port mapping adds delta delay as well, but as it is done for all the ports, together with the clock, still they are sync with each other (all of them are delayed by 1 delta cycle).
Hi, is it a fair statement to say that there is a mismatch between simulation and HW behavior if the code is not written in a synthesizable way according to the guidelines of the manufacturer of the FPGA? If you really want to expose mismatches, I think you should at least follow those guidelines, otherwise the synthesizer SW cannot guarantee that the semantics of the code is preserved between simulation and implemented HW.
Yes, there may be mismatches between the simulation and the implementation if the code isn't written according to conventions and guidelines. But the mismatch I showed in this video doesn't mean the synthesis tool is wrong or bad. It just follows the convention that all or most synthesis tools use for generating netlists from VHDL code. It's important to be aware of that.
So, my guess is that when we do port mapping, it does not add delta delay. Am I right?
I mean when we instantiate a component and do port map for that. Because if it's going to add delta delay, then when we port map the clock of a component to the clock of the top level (which is a quite common practice), then inside that component will not be in sync (from delta cycle clock point of view) with the top level anymore.
Or it could be that port mapping adds delta delay as well, but as it is done for all the ports, together with the clock, still they are sync with each other (all of them are delayed by 1 delta cycle).
Hi, is it a fair statement to say that there is a mismatch between simulation and HW behavior if the code is not written in a synthesizable way according to the guidelines of the manufacturer of the FPGA? If you really want to expose mismatches, I think you should at least follow those guidelines, otherwise the synthesizer SW cannot guarantee that the semantics of the code is preserved between simulation and implemented HW.
Yes, there may be mismatches between the simulation and the implementation if the code isn't written according to conventions and guidelines. But the mismatch I showed in this video doesn't mean the synthesis tool is wrong or bad. It just follows the convention that all or most synthesis tools use for generating netlists from VHDL code. It's important to be aware of that.