The Case For Chiplets
Вставка
- Опубліковано 11 лип 2024
- Kandou’s Amin Shokrollahi talks with Semiconductor Engineering about what’s behind the momentum for a LEGO-like approach, where the challenges are, and how the cost compares with other approaches.
- Наука та технологія
Wonderful overview of Chiplet technology. He is also the father of Fountain Codes and certain LDPC Codes.
in the future, at least for the end user market, you will have the RAM directly in the CPU using HBM memory architecture. The system bus will communicate serially with the peripherals to save packaging costs.
Memory size requirements are becoming negligible through cloud computing, but low power consumption is becoming increasingly important. Laptops are becoming more standard and will displace the desktop in 10 years.
Laptops are fragile, expensive to repair and have limited upgrade potential. Good high performance ones are also expensive. There are great 35W CPU but Intel's latest desktop consumer CPU can use 10x those watts and they get away with it. Sapphire Rapids uses 500W and struggles to match AMD's Zen3 Threadripper Pro despite faster DDR5. A lot of people simply don't care about power consumption.
That's a good sharing. Could you help me to shed some lights here, what are those final checks for the Chiplets, in order the chip to work functionally?
Hi, you may want to check out the chiplets knowledge center here semiengineering.com/knowledge_centers/packaging/advanced-packaging/chiplets/.
Appears AMD will do chiplets which will allow them to use the same chiplets for the PC and Console markets. Genius. We are about to see GTX 1080 level chiplets with consumer processor chiplets for at relatively amazing prices
My understanding on GPUs for gaming we won't see a chiplet design as it amounts to SLI or crossfire and we all know how well and wide those features were implemented. So 7nm NAVI is not likely to go that route though for things like ai we will see that approach taken.
Im not quite convinced that chiplets will continue the improved processing power of cpu from gen to gen. The chiplets will still be at 7nm for example. But the chiplets will be very far apart compared to standard layout of a mono die. High bandwidth interconnection? Please, it will never be as good as mono die. Increased yield is good for chip mfg and the end consumer. But end consumer is not so conserned with low yield, they just assume the chip mfg will just eat it and keep making moni die especially when chip mfg has tough competition from other chip mfg. Either switch to another substrate, exotic architecture design or keep reducing mfg node below 7nm. Am i right?
Really? That's already aged badly, Ryzen x3D V-cache stacking was able to triple L3 cache size with IIRC a single cycle latency increase mixing 7nm cache optimised L3 die with 5nm CCD and a 6nm IOD.
If you look at Sapphire Rapids and Zen4 Threadripper you'll see Intel's monolithic is no smaller and it's the Zen4 chiplets that have higher power density. Thermodynamics mean cores have to be apart.
Chiplets allow AMD to make CPUs that Intel cannot match eg) 12x8c & 8x16c, while Intel are introducing their stacked tiles in 2024 to the consumer market.
If monolithic was so superior Ryzen couldn't succeed in the consumer market using CCD chiplets primarily designed for the server market.
Using different IOD, V-cache and CCD AMD cover a wide range of CPU applications, reusing 2 IOD & 2 CCD designs, while monolithic versions still follow for mass market price sensitive niches.
Consumers like low prices, so design cost efficiency and buying lower quality dies, with a generous cache is good enough at hiding latency. That L3 is closer to the cores than in mono
IP's on different chips? Marketing fluff.
IPs on different chips is a significant issue. It can impact overall system/package performance, power/thermal management, integration time and overall cost, and it can affect everything from electrostatics within a package to competitiveness in various market segments. This is a particularly difficult issue to solve when it comes to IP developed at different process nodes, with in-house vs. commercially developed IP, and with black-box IP where you have to take the word of the vendor on characterization.
Are you suggesting that IPs on different chips is somehow a new thing?
No, but the ability to mix and match without worrying about which node at which IP was developed has never been done on a mass scale. This is basically a balancing act between faster time to market and customization. Whether it works or not isn't clear, but it's going to be interesting to see if a commercial marketplace for hard IP develops with the necessary level of detail. Still not clear is who will run that marketplace or what it will look like (by market, node, region, open-source vs. proprietary, etc.)