I can't believe I just found such a course on YT and for FREE! Thanks a lot for sharing it, I really appreciate the clarity of your explanations and the details you have covered in this course.
This is perhaps the best Vitis Video I have every seen. Its an undergrad course but very suitable for practicing FPGA engineers like myself. No exaggeration intended. I have shared this video series with my cofounders in 3 different startups. This video series should be converted into a Coursera or Udemy program for those who already exp. with Verilog or Sys-Verilog or VHDL. Along with the free book from Prof. Castner & his UCSD team.
There are measures proposed for HLS based design by other authors. The theoretical best ones are from Prof. Keshav Parhi at Univ. of Minnesota. First measure is the Iteration bound . Computation time of each loop divided by the delays in each loop. Maximize this ratio over all K loops. This measure is due to Parhi. Parhi provides a Matrix method to compute the iteration bound.
Does all of the 1000s of lines of Verilog code @5.30 in the video need to be generated by hand or is a lot of it boilerplate code that can be automatically generated? Thanks for the great video 👍
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
I can't believe I just found such a course on YT and for FREE!
Thanks a lot for sharing it, I really appreciate the clarity of your explanations and the details you have covered in this course.
This is perhaps the best Vitis Video I have every seen. Its an undergrad course but very suitable for practicing FPGA engineers like myself. No exaggeration intended. I have shared this video series with my cofounders in 3 different startups. This video series should be converted into a Coursera or Udemy program for those who already exp. with Verilog or Sys-Verilog or VHDL. Along with the free book from Prof. Castner & his UCSD team.
You're a genius man. You're helping me out a lot in my PhD!
I have Embedded system Engineering course in masters MSC.Thanks for the video.Sincerely.
There are measures proposed for HLS based design by other authors. The theoretical best ones are from Prof. Keshav Parhi at Univ. of Minnesota. First measure is the Iteration bound . Computation time of each loop divided by the delays in each loop. Maximize this ratio over all K loops.
This measure is due to Parhi. Parhi provides a Matrix method to compute the iteration bound.
Thanks for your upload
Thank you for the clear and perfect explanation
AWESOME VIDEO
Thank you for the upload
Does all of the 1000s of lines of Verilog code @5.30 in the video need to be generated by hand or is a lot of it boilerplate code that can be automatically generated?
Thanks for the great video 👍
안녕하세요 교수님 혹시 한국어 강의도 있을까요?
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
I am not too sure, but Vitis Vision Library seems to be supported on Vitis 22.2.
How come verilog is censored in the video? Proprietary?
No, I was just making a point that a Verilog design is less readable than an HLS design :)
Could you share lecture slides?
Sorry for the late reply - uploaded to my website at sites.google.com/view/ykchoi/teaching
@@youngkyuchoi4260 Thanks