Hi Sir, thanks for the explanation. Is it in your comparison the inductance and capacitor values equal for the single phase and the multiphase converter? I have been confused about the components design on these multiphase converters. I found that the inductor selection equation, as a function of the current ripple, is the same for one phase that for multiphase. From reducing parallel inductances, if the inductances are equal, the equivalent inductance (Leq=L/N) shall be reduced by a factor of "1/N". So "1/N" shall be part of the formula, right? Similarly, the capacitor equation, as function of the voltage ripple, is the same for the single phase and for multiphase. Is it like an exor factor reduction? I mean, I should reduce the inductor value by 1/N or, exclusively, reduce the capacitor value by 1/N exor to the duty cycle (Ton) exor the frequency? regards! :)
Multiphase converters on cpu applications are trending towards TLVR topology. Have yet to see an intuitive explanation on how those converters work. Do you plan on having a video explaining those?
Do you just what to know if I am planning or do you want to watch such a video😊Thanks for the suggestion. Good topic that indeed needs clarification. Planning to develop o video on that.
I have never plotted measured results in ltspice. I did not know that was possible. Learning that is possible is the best thing I learned from this. Thank you. p.s. Why do the measured results end up in the error file?
Sam, would you agree we cannot use synchronous busk in an interleaved configuration as one converter drives current into another? Do you afree? If not why not?
With so many synchronous interleaved Buck converters built, it does not matter if I agree or not. See for example www.matec-conferences.org/articles/matecconf/pdf/2020/10/matecconf_icsc-isatech20_02005.pdf
@@sambenyaakov I am staggered with article. 270V in & 28V out the duty cycle is 10% i.e. Two of the sync switches are ON for 90%. More current flows into buck inductor tha out i.e. 10% ON & 90% OFF. The sync transistors act like a BOOST transistors when turned OFF !!!!
@@dipakpatel9329 Yes, but each converter has its own current control loop. Eventually, the duty cycles will be adjusted to conter the ill effect - boost operation.
@@nachiketadeshmukh8444 3 current loops, this is new one on me. Whole idea is they share equally. My question is if sync fet is ON for 90% at low load,will current flow into inductor and into switch> Than what happens?
Dear Sir. The offline SMPS are continuing on size reduction due to several technological aspects. But, the main rectifier+input filter capacitor are becoming a comparative hindrance for this size reduction. Could you expose some Main Rectifier+input filter reductions strategies alternatives? Regards.
@@sambenyaakov I mean the capacitor after the rectifier. I mean: the input rectifier plus the following bulky capacitor (one-phase 50/60Hz sinal handling) is comparativelly bulky.
I am yet to see this video, but if it Sen Ben yakov, it is bound to be great learning while watching.
😊👍
Hi Sir, thanks for the explanation.
Is it in your comparison the inductance and capacitor values equal for the single phase and the multiphase converter?
I have been confused about the components design on these multiphase converters. I found that the inductor selection equation, as a function of the current ripple, is the same for one phase that for multiphase. From reducing parallel inductances, if the inductances are equal, the equivalent inductance (Leq=L/N) shall be reduced by a factor of "1/N". So "1/N" shall be part of the formula, right?
Similarly, the capacitor equation, as function of the voltage ripple, is the same for the single phase and for multiphase.
Is it like an exor factor reduction? I mean, I should reduce the inductor value by 1/N or, exclusively, reduce the capacitor value by 1/N exor to the duty cycle (Ton) exor the frequency?
regards! :)
The equation is per an inductor ripple you specify
Multiphase converters on cpu applications are trending towards TLVR topology. Have yet to see an intuitive explanation on how those converters work. Do you plan on having a video explaining those?
Do you just what to know if I am planning or do you want to watch such a video😊Thanks for the suggestion. Good topic that indeed needs clarification. Planning to develop o video on that.
Thanks for uploading a video on initiative explanation of TLVR buck converters. Really simplifies the working! 👍
@@anmolshah6838 Thanks
I have never plotted measured results in ltspice. I did not know that was possible. Learning that is possible is the best thing I learned from this. Thank you.
p.s. Why do the measured results end up in the error file?
Why do the measured results end up in the error file? they did not find another place for it😊
Hi Sir great lecture...could you please make a lecture on hold-up circuit using supercapacitor?
Hi professor, there is something wrong on the page 26 of your PPT: you use rms_out_mul/rms_in_singleL. Should be rms_out_mul/rms_out_singleL.
Hi, thank you very much for your observation. I will put a note on this error in the description section of the video.
Sam, would you agree we cannot use synchronous busk in an interleaved configuration as one converter drives current into another? Do you afree? If not why not?
With so many synchronous interleaved Buck converters built, it does not matter if I agree or not. See for example www.matec-conferences.org/articles/matecconf/pdf/2020/10/matecconf_icsc-isatech20_02005.pdf
@@sambenyaakov I am staggered with article. 270V in & 28V out the duty cycle is 10% i.e. Two of the sync switches are ON for 90%. More current flows into buck inductor tha out i.e. 10% ON & 90% OFF. The sync transistors act like a BOOST transistors when turned OFF !!!!
@@dipakpatel9329 Yes, but each converter has its own current control loop. Eventually, the duty cycles will be adjusted to conter the ill effect - boost operation.
@@nachiketadeshmukh8444 3 current loops, this is new one on me. Whole idea is they share equally. My question is if sync fet is ON for 90% at low load,will current flow into inductor and into switch> Than what happens?
Dear Sir.
The offline SMPS are continuing on size reduction due to several technological aspects. But, the main rectifier+input filter capacitor are becoming a comparative hindrance for this size reduction. Could you expose some Main Rectifier+input filter reductions strategies alternatives? Regards.
You mean the capacitor after rectification? or capcitor(s) of the input filter between line an APFC?
@@sambenyaakov I mean the capacitor after the rectifier. I mean: the input rectifier plus the following bulky capacitor (one-phase 50/60Hz sinal handling) is comparativelly bulky.
@@JorgeSilva-em8pf Got it. I consider the preparation of a video on capacitance multipliers.
👍🙏❤
👍😊🙏