Interfaces, AXI Bus, AXI Interconnect , Digital System Design 2018 Lec 6/30 [Urdu/Hindi]

English version: • The AXI Protocol, AXI ...
Topics Covered:
- Review 0:00
- Interfaces 3:10, Flow control - from master 5:44, from slave 7:03
- Serial and differential interfaces 12:20
- Memory mapped devices/interfaces overview 16:25
- Processor Buses 21:00
- Single Master-Slave Memory mapped interface 22:44
- Multiple Slaves 29:03
- AXI Stream Interface 33:44
- AXI Interface 41:52
- AXI Interconnect 45:27
- Vivado AXI Naming conventions 57:24
- AXI stream-mem-map conversions 1:03:12
- AXI Lite vs AXI-Full (Single beat vs Burst) 1:14:40
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This course is taught at Abasyn University Islamabad, Fall 2018
www.abasynisb.edu.pk/
Renzym is a technology company.
www.renzym.com

[@08bharadwaj]

Excellent apne language me sikhne ka mazaa aur hi he

[@akhileshgoyal7565]

Thnku sir, wht a way to teach seriously amazing.....

[@saileshbissessur]

Great way to present. Very well explained.

[@Brekhna]

Loved the 'chota' analogy.. :D

[@DD-sm2gz]

Thanks a lot sir.

[@akhileshgoyal7565]

sir i request u to plz upload APB,AHB, protocols videos

[@RenzymEducation]

English version (and a bit shortened with more signals covered): ua-cam.com/video/Ko3wmIVsOtM/v-deo.html

[@akhileshgoyal7565]

can u upload STA related videos

[@bharatagarwal6330]

Sir can you please help me out in one of my project . I want to use XADC of the ARTY FPGA and i will be giving the 20 KHz sine wave to ADC externally using function generator and after sampling I want to store data in external file or inside BRAM of FPGA so that i can take that sampled data in MATLAB and can perform FFT with my transmitted signal .
Please also tell how I can put .txt file data in FPGA.

[@RenzymEducation]

I haven't used XADC yet. I would look for some App note or demonstration video from Xilinx to start with like ua-cam.com/video/aLrOvtZkM0s/v-deo.html if I had to implement such a design
For second part, you can initialize a Block RAM with data from a text file. I demonstrated this in another video
ua-cam.com/video/-oUZEZKxL6A/v-deo.html
But there are multiple ways depending on how you create a block RAM.
a) If you are using "device primitive" form "language template" then you can directly write data in initialization.
b) Alternatively you can use "coding example" from "language templates" and in that case you can specify a text file containing hex data.
c) Similarly in block RAM generator in Vivado you can provide a coefficient file while generating IP containing data.
d) All above options will initialize BRAM with fixed data. If you want to change data then you will have to take data from some interface (USB/LAN/PCI etc) and write in through one port
e) If you are using a Zynq based system then instead of block RAM you can write to DDR memory instead. You can initialize DDR sections using Dump and restore option in XSDK. ua-cam.com/video/nyQBj-VNZ3c/v-deo.html

[@rkbarik619]

Is there any link to the previous lecture that you are talking on this particular video!!!!!!!!!!!!!!!!!!!!!

[@RenzymEducation]

Here is the link to complete playlist starting at previous lecture
ua-cam.com/video/m_1Zf6P923M/v-deo.html

[@sridevia4819]

Kindly put the videos in english sir

[@RenzymEducation]

I will start that probably in around a month

[@RenzymEducation]

I finally uploaded English version: ua-cam.com/video/Ko3wmIVsOtM/v-deo.html

[@sridevia4819]

@@RenzymEducation Thank you very much sir