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We_LSI
India
Приєднався 10 сер 2023
Hello VLSI enthusiasts...
Welcome to my We_LSI ! This channel is here to help you learn Verilog, SystemVerilog, and UVM.
You can find verilog and system verilog videos here. Planned to cover complete system verilog concepts and also some of the protocol videos. These videos are mainly for freshers and those who are new to system verilog. I might have missed few points while explaining but please make sure to clear your doubts at that instant only.
"It is what we know already that often prevents us from learning" ^_^
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“You don't need more time, you need more focus”
Welcome to my We_LSI ! This channel is here to help you learn Verilog, SystemVerilog, and UVM.
You can find verilog and system verilog videos here. Planned to cover complete system verilog concepts and also some of the protocol videos. These videos are mainly for freshers and those who are new to system verilog. I might have missed few points while explaining but please make sure to clear your doubts at that instant only.
"It is what we know already that often prevents us from learning" ^_^
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“You don't need more time, you need more focus”
Covergroup,Coverpoints and Bins| PART-2 | in #systemverilog #vlsi #verification #learning #tutorial
Covergroup,Coverpoints and Bins| PART-2 | in #systemverilog #vlsi #verification #learning #tutorial
Переглядів: 215
Відео
Systemverilog Coverages Intro| PART-1 | #systemverilog #vlsi #verification #learning #tutorial
Переглядів 56321 день тому
Systemverilog Coverages Intro| PART-1 | #systemverilog #vlsi #verification #learning #tutorial
Clocking block with examples in SystemVerilog #vlsi #verification #coding #systemverilog #learning
Переглядів 391Місяць тому
Clocking block with examples in SystemVerilog #vlsi #verification #coding #systemverilog #learning
Examples for Interface,modports and virtual interface in SystemVerilog #vlsi #verification #coding
Переглядів 4832 місяці тому
EDA Playground Links for the Above examples: www.edaplayground.com/x/VRBb www.edaplayground.com/x/WKEx www.edaplayground.com/x/T8bN
Modports in SystemVerilog #systemverilog #vlsi #verification #semiconductor #education #learning
Переглядів 5762 місяці тому
0:01 :Introduction 4:03 :Importing and exporting methods 7:00 :Restrictions on exporting task/functions
Interface and virtual interface in #systemverilog #vlsi #verification #tutorial #semiconductor
Переглядів 1,2 тис.3 місяці тому
0:20 :Introduction 3:21 :Example - Without interface 3:55 :Example - With interface 6:15 :Notes for interface 8:27 :Generic interface 10:42 :Tasks and functions in interface 12:35 :Notes for functions and tasks in interface 17:19 : virtual interface
Program Block PART - 3 in Systemverilog #systemverilog #vlsi #verification #tutorial #semiconductor
Переглядів 7553 місяці тому
EDA Code link: www.edaplayground.com/x/exSP 0:17 :Introduction 7:31 :Key points of program block 12:08 :Similarities between module and program block 13:08 :Differences between module and program block
Program Block PART - 2 in Systemverilog #systemverilog #vlsi #verification #tutorial #semiconductor
Переглядів 7254 місяці тому
0:17 :Introduction 7:31 :Key points of program block 12:08 :Similarities between module and program block 13:08 :Differences between module and program block
Race condition and Event scheduling in #systemverilog #vlsi #verification #tutorial #semiconductor
Переглядів 1,3 тис.4 місяці тому
Race condition and Event scheduling in #systemverilog #vlsi #verification #tutorial #semiconductor
Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor
Переглядів 2,4 тис.7 місяців тому
Examples for Constraint #systemverilog | PART-1 |Constraints Q&A #vlsi #learn #coding #semiconductor
Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn
Переглядів 1,1 тис.8 місяців тому
Constraints in #systemverilog | PART-8 | rand_mode and constraint_mode in constraints #vlsi #learn
Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn
Переглядів 1,4 тис.8 місяців тому
Constraints in #systemverilog | PART-7 | Bidirectional and Solve-before constraints #vlsi #learn
Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint
Переглядів 1,2 тис.8 місяців тому
Constraints in #systemverilog | PART-6 | implication operator and if-else construct in constraint
Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi
Переглядів 1,6 тис.9 місяців тому
Randomization and Constraints in #systemverilog | PART-5 | with and soft keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi
Переглядів 1,9 тис.9 місяців тому
Randomization and Constraints in #systemverilog | PART-4 | dist keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi
Переглядів 1,7 тис.9 місяців тому
Randomization and Constraints in #systemverilog | PART-3 | inside keyword in constraint #vlsi
Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi
Переглядів 2,3 тис.9 місяців тому
Randomization and Constraints in #systemverilog | PART-2 | inside keyword in constraint #vlsi
Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification
Переглядів 3,5 тис.9 місяців тому
Randomization in #systemverilog | PART-1 | Introduction to #randomization| #oop #vlsi #verification
Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor
Переглядів 1,6 тис.9 місяців тому
Scope resolution operator in #systemverilog | Introduction & Examples| #verification #semiconductor
Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Переглядів 2 тис.10 місяців тому
Virtual class in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Переглядів 2,1 тис.10 місяців тому
Virtual keyword in #systemverilog | Introduction & Examples| #verification #verilog #semiconductor
Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi
Переглядів 2 тис.10 місяців тому
Mailbox in System verilog | Part 2 | Examples| #systemverilog #vlsi
Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi
Переглядів 2,8 тис.10 місяців тому
Mailbox in System verilog | Part 1 | Introduction | #systemverilog #vlsi
super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor
Переглядів 2 тис.10 місяців тому
super keyword in #systemverilog |Introduction & Examples|#vlsi #verification #verilog #semiconductor
this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor
Переглядів 2 тис.10 місяців тому
this keyword in #systemverilog | Introduction & Examples|#vlsi #verification #verilog #semiconductor
Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv
Переглядів 1,8 тис.11 місяців тому
Inheritance in #systemverilog | PART-2 | Examples for #inheritance | #oop #vlsi #verification #dv
Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification
Переглядів 2,3 тис.11 місяців тому
Inheritance in #systemverilog | PART-1 | Introduction to #inheritance | #oop #vlsi #verification
Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog
Переглядів 2,9 тис.11 місяців тому
Static class members in System verilog | PART-1 | Static properties & methods in #systemverilog
Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog
Переглядів 3,4 тис.11 місяців тому
Classes in System verilog | PART-2 Examples |#classes in #systemverilog | OOPs in system verilog
Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog
Переглядів 9 тис.11 місяців тому
Classes in System verilog | PART-1 Introduction |#classes in #systemverilog | OOPs in system verilog
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Nice explanation thank you
Thank you!
Hey guys, Sorry. There is a mistake in explicit bins at time: 14:15 when size is not fixed for vector bins, number of vector bins = number of elements when there is no 'range' in the set. if 'range' is there in the set then automatic bins will be created for the all values in the range. so in the ppt for addr b2[ ]={[2:9],11}; total 9 bins will be generated. i.e. b2[2] to b2[9] and b2[11]---> total 9 bins Please note it. And the same will be explained in the next example video.
Madam please can u please share ppt of verilog and system verilog madam It could helpful to review or to practice
Yes I will share the ppt folder soon.
@@susheelapatagar thank you madam
Mam please upload parammeterized classes
Okay.
Even my trainer didnot teach as well as u.......thnx u soo much susheela.....❤
@@SaikiranReddy-c8p Thank you 💛
Nice explanation with sweet voice ❤
@@yashwanthgade4854 Thank you 🩵
Very helpful Thank you miss
@@Zumbagaming2 Glad to hear✨
appreciate your initiative kudos
@@akshatamugalihal1850 Thank you!
i have one doubt mam, in ordering methods ,once any changes are done to the array and if we want to perform the next ordering method ,it is considering the previous resulted one ,how to consider the declared array for all the ordering methods
@@akhilrachagundla757 Yes, you can declare a new array and assign the original array to it. Perform the operation on the newly declared array to ensure the original array remains unaffected, allowing it to be used for another method. Ex: int array[8] = '{2,1,7,3,1,8,9,6}; int arr_1[8], arr_2[8]; initial begin arr_1 = array; arr_1.sort(); $display("after sort------>%0p",arr_1); arr_2 = array; arr_2.shuffle(); $display("after shuffle------>%0p",arr_2); end
I am new to here but want to learn completely from beginning from where should I start
@@hardiksingh2799 Great. You can start watching in this order: 1. System verilog basics: ua-cam.com/play/PLcmfUkZaXr_yssjVbupeUC9N2B7UnMjY1.html&si=hj9i9UckzJHhnKvr 2. Classes: ua-cam.com/play/PLcmfUkZaXr_wwYi0cuPnpUAadmpmD827L.html&si=8Yv3Ao-HGMEAlL3e 3. IPC: ua-cam.com/play/PLcmfUkZaXr_zox8y0WEVWQ9hiNeCmuxFy.html&si=r1IG7F39JkTOi2IS 4. Coverages: ua-cam.com/play/PLcmfUkZaXr_wj4NCRC_QgD-oxs-Kk31GY.html&si=3VdP8RUx7zW4f2-5 I have not covered some basic topics like introduction and data types, as you can find resources for those on various websites. Additionally, the SystemVerilog series on this channel is still ongoing, so stay tuned for more videos!
Good evening Maam
mam ,pls upload videos on FORK-JOIN and it variations and physical & virtual interface
@@malikchilakala7865 I have already uploaded videos on fork-join, interface and virtual interface. Please check all the playlists.
Nice video Int datatype in 2 state
Thank you. Yes forgot to add int type in 2 state.
Mam assertion video madi bega
@@rohans939 Madtini. Coverage admele next series Assertions e.
Madam please can u please provide any ppts or hand written notes of pdf for system verilog and verilog sir , it may help to understand like me to all thee members madam
@@bhaskarsharma6520 I don't have written notes but I can share the ppts. I will add the PPT folder link soon.
@@susheelapatagar thank madam Thankyou very very much madam
Waiting the lot for it.....thank you madam......
@@SaikiranReddy-c8p Welcome!
Please upload videos on assertions madam
@@Zumbagaming2 Yeah I will upload. Before that I need to complete coverages.
Please upload more videos about SV regions and constraint questions it's a humble request
@@Zumbagaming2 Yeah. I have already covered sv regions and constraint questions will be available in shorts video. Please checkout "interview questions" playlist.
Very useful ❤
@@sivaprasadpk244 Happy to hear that ✨
Great lecture mam😊
Thank you💛
Contents that you're teaching are literally too good. Keep doing many videos, could you please share the notes if possible.
Thank you. I dont have notes but I can share the ppt if you want. susheelarpatgar@gmail.com
U r the best mam keep going
Thank you.😍
Ma'am your way of teaching is awesome please don't stop making videos there very less teachers making vlsi content. Its our job to support you please don't give up
Thanks for the support🥰
Hi susheelaa, PRESETn from the system bus right, here what exactly means system bus??
Here system bus just means that PRESETn signal is niether coming from master nor from slave. Its directly connected to system bus (APB interface)that carries data,address and control information. if source is Requester, then specified signals are coming from master device. If source is completer, specified signals are coming from slave device.
mam do sv asserstion and uvm
@@sumanthn3277 👍
Good
@@molakasravani6574 Thank you.
You are supper madam
❣️👍
Great information easy to understand
Thank you.
In the 1st difference if we use logic datatype then answers for y and z are same. can u explain about diff b/w using int and logic in this example
Reason: always @(a) --> if a is logic,default value of a=x. and initially we have assigned a=0; thats why a is transitioning from x to 0. So always block got triggered. When we use int type, default value of a=0. and in the initial block also we have assigned a=0 initially. So no transition is made & didn't trigger the always block. So the difference is because of the type of a signal.
Thank you ❤
💜
Great👌 i have a question-Can you please give a logic to find second largest element in an array without using array methods
@@hareeshvs8845 class packet; rand bit[4:0]a[]; bit[4:0]b[]; constraint c1{a.size == 5;unique{a};} function void post_randomize(); b=new[$size(a)]; b={a}; for(int i=1;i<$size(b);i++) begin if(b[i]>b[i-1])begin b[i] = b[i] + b[i-1]; b[i-1] = b[i] - b[i-1]; b[i] = b[i] - b[i-1]; i=0; end end foreach(a[i])$write("%0d ",a[i]); endfunction endclass module gen_pattern; packet p; initial begin p=new(); repeat(5)begin p.randomize(); $display("2nd largest==%0d",p.b[1]); end end endmodule //Or just generate descending order array and print 2nd element
Good👌👌
@@hareeshvs8845 Thank you:)
mam explain how to generate two conscutive ones for 16 bit variable
Ok. I will upload one short video for this question.
Very nice explainatino. Thank you so much
@@VellaHere Thank you:)
ma'am eda link?
Please check the description.(Updated the link)
Tq ma'am 😍
Please post new video mam waiting for your explanation thank you @@susheelapatagar
@@poojithaontipalli9616 Thanks for your patience! I’m dealing with a few issues, but I’m working on it. Video will be available shortly, and I truly appreciate your support! Thank you.
mam provide some more practice questions
@@shivaibara4733 checkout my 'community' section in Home page for quiz and constraint questions.
Could you make a video about how to use run.do or run.bash on eda playground, please? Many thanks.
@@ngocmanprocoder Sure. Wait for my coverage videos. There I will be using run.do files for coverage report.
mam please give the mail and password for EDA tool accesss
@@shivaibara4733Sorry I can't share my login credentials so If you have your college id or office ID you can use it for EDA access.
@@susheelapatagar ok mam