Відео

"Think of it as designing a circuit and not a sequence of instructions" Dope

based and vim pilled

This is one of those topics where only a fairly small amount of people learn about it every year, and videos like this wouldn't get many views. For those who do watch this (me) and have to learn (also me) this, it is extremely helpful and I really appreciate you taking the time to explain this in a simple way so that one can grasp this in the right way from the beginning. Thank you!

Very good explanation Thank you 😊

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For creating a clock by process, you should have inserted one line of code after wait For 5 ns : signal a : std_logic := '0' process begin a <= not (a) ; wait for 5 ns ; a <= 1; end process ;

thanks for this as someone returning to electronics for my hobby of 9 bit micros i have not sued one for decades , so this really bought it all back for me

So its not possible to add breakpoint into code when using teh GHDL, is this correct?

When I was earning my master's degree, I heard a lot about finite state machines (FSMs), but it was all theory - like clouds in the sky: there's a lot of water, but you can't drink it. I toiled for three months after graduating until I implemented my first FSM in code in 1981. Now, there is a programming methodology based on this concept - v-agent oriented programming (VAOP) - with many examples of its implementation. It's best to start learning about VAOP with this article on Medium: "Bagels and Muffins of Programming or How Easy It Is to Convert a Bagel into a Black Hole".

Beautiful. Got an exam tomorrow, helped a lot. Thank you.

Superb!

VHDL process is a lie: it doesn't exist 🤪

Will you provide a link to sevenseg.vhd or a UA-cam video where you create it so I can get the last step of the simulation to work? Great video BTW!

how do we know that the output stays high when both the clock and A go low at the same time?

thank you for your time

Why must I even think about VHDL ? 🤪

Should have used a laser pointer, or a fixed focus camera

Thank you omg

Dude thank you so much. I have an exam tomorrow, this was lifesaving. I subbed and liked🙏🏽

Don't we have to initialize the states?

Hi! What if i have 3 states in my diagram? can i still use the two bits representation? 00 01 10 11? I won't have to use one of them tho. help please

Although ... for a proper A => B with 3 values, you need a LUT with *9* entries ... hrm

3-LUT are cool for directly implementing #RM3 implication. Electronic logic circuits these days are already non-binary, with at least "true", "false", and "don't care" (X). The logical value of "Both true and false" is equivalent to "neither true nor false" so you only need 3 values, really.

nice video

Been at this language for a while and I still pull my hair out on occasions, but lately its all been coming together since using component imports and generics, I tend to think of designs in terms of counters and glue logic, i.e. state machines, if you try and fall back on VHDL doing the power tasks without thinking in terms of hardware behind it, you will create some monstrously bulky designs, KISS method. When you start, dont make the same mistake as I did, when you search for help, ALWAYS make sure the examples are SYNTHESIZABLE (can be programmed into hardware) or testbench which cannot, learn one first, not both at the same time or you might go mental!

thank you!

lip smacking is very distracting

Thank you for clear explanation. I think there is an issue. in this line ( hourplus <= "0" & hour;), I think you should use OR(|) instead of AND (&).

Which VHDL editor can I download for free

What is it about the radiant that makes it not great as you put it?

Thank you for taking the time to make this video. Much appreciated.

Thanks just what I needed. Great video

Hi, i have experience with Ladder Logic. Do you think this would give me an advantage in learning VHDL?

By far the clearest and both concise on YT. Thanks!

Hello

❤

Hi, i think there is a mistake in the S0 KMAP 11:44 . 0110 is a minterm, but you accidentally put it as 0.

not in your class but going through the paces in CompE, thanks

Thank you

thanks!