Simulating VDHL code with GHDL

Поділитися
Вставка
  • Опубліковано 29 гру 2024

КОМЕНТАРІ • 8

  • @marciomaiajr
    @marciomaiajr 3 роки тому +6

    Just found your channel. Awesome content. Theres not much stuff about GHDL on the Internet.

  • @優さん-n7m
    @優さん-n7m 6 місяців тому

    So its not possible to add breakpoint into code when using teh GHDL, is this correct?

  • @stephanbokelmann507
    @stephanbokelmann507 2 роки тому

    Where does the file sevenseg.vhd come from.... am I missing somethin?

    • @botsnlinux
      @botsnlinux  2 роки тому

      I'm assuming that it's a VHDL module in a separate file that's already been created -- in my course most students have already built this for their lab project before they start simulating stuff. Any module with a matching entity declaration will work with this example testbench.

  • @SandwichMitGurke
    @SandwichMitGurke 3 роки тому

    when i run the Makefile, i get this warning:
    instance "dut" of component "sevenseg" is not bound [-Wbinding]
    Do you have a sevenseg file in that folder or have you compiled a sevenseg entity before running this?

    • @botsnlinux
      @botsnlinux  3 роки тому +1

      Yes, this assumes that there's a file `sevenseg.vhd` which has to be analyzed/included in the design (I add it to the Makefile around 6:25)

  • @SandwichMitGurke
    @SandwichMitGurke 3 роки тому

    very helpful, thanks