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Depends on the error, if the error due to RTL files, RTL DESIGNER needs to update the latest version of RTL files and provide it to Synthesis Engineer

It is clearly mentioned in the video that Spef is an optional input to Physical synthesis which contains parasitic data for wires in a chip to meet timing and avoid signal integrity issues

@@EngineerVijitaaDas mam may i know at which stage spef file is generated...

​​after routing stage. But floorplan and placement has to be good. As SPEF file contains R and C parameters, which depend on the routing and placement of the cells and tiles. This file is used to accurately calculate IR-drop analysis and other analyses after routing. This data is important to consider because non-ideal wires have parasitic resistance and capacitance. Physical synthesis is a process that takes into account late-stage implementation effects early in the design process. The goal is to create a design flow that requires minimal rework. Physical synthesis considers effects like wiring, parasitic effects, and long wires. These are iterative process but with few iterations, results can be achieved as targetted. After spef is generated, if we still see SI related issues, we can use the spef as input to Physical Synthesis flow at compile stage. Then synthesis tool is now aware of RC data, so tool doesn't have to estimate using WLM. Thats why designer use spef. Hope this explanation clears your doubt. Thanks

@@EngineerVijitaaDas thankyou alot🙏 mam🙂....after completion of routing stage we generate spef file and this spef file is now used in physical synthesis process right (if spef is required)

@@kv8536 yes based on violations and issues faced by the designer

Yes, soon

I will do a detailed inputs to PD video.

Thanks

@@EngineerVijitaaDas can you please do video on data to data checks, it's very useful for all

@@User--jm5916 sure i will

Glad to hear that

I am not sure about that.

Can you please share important questions for PD

@@AffectionateGo-Kart-hq7iy will share in a separate post. Mostly the videos I posted till date are commonly asked questions in PD

Thank you so much

Its my pleasure. Stay tuned to the channel

Definitely will post

Based on optimization we can use clock inverter and buffer. Not necessarily throughout design we have to use any of them... we can use both in a same design. To save area, the first buffer is typically of a lower drive strength and is placed very closed to the second inverter. Since different drive strength so pulse width is not same. Advantage of using inverter based clock tree is that the high pulse and the low pulse width would be symmetrical.