Відео

Can it mine crypto this board ? Can it be programmed to mine crypto coins for different algos ???

I have stupid question. How can I use JTAG/UART in JTAG mode? Do I need special cable? When I connect normal USB data cable, UART part works, I can see comms but not getting any JTAG connection in Vitis. Could you please dumb it down for me how I can use USB JTAG/UART to program FPGA logic and SoC?

@FPGA Zealot - can you do some video where you make FPGA miner for kawpow, ethash and other useful most popular algos? How to make a bitstreams from mining algos - can you make some awesome video please ??

I noticed u dma'd up to what was available in the bar ( 1MB ) how would you dma 'the rest' ( 4GB ) Is there a way to shift with that 8648 register perhaps to get more of the DDR? 1:16:01

Hello, if we have trained a custom CNN model for a particular application with a dataset on colab as model file and h5 file , could we implement the model in vitis ai , if so could you please provide a tutorial on that , it would be extremely useful thankyou

CNN on Pynq

please do more videos using nios v processor sir

Hi is it possible to do this installation if I have wsl

Another incredibly helpful stream. I was able to replicate pretty much all of this with 2024.1 toolchain and on a different versal part (VD100 from Alinx) down to every Vitis bug , the only things left is actually running it. Seems that booting your pdi with baremetal elf is the hardest part to get right (until you figure it out, that is). Also, the most important detail about linking aarchnone64.o - it would take forever if you didnt point it out.

i would be very interested if you can expand on this exercise - to run Linux (minimal) on a NIOSV soft-cpu on a DE0-NANO or other small board board. :)

I didn’t even know there’s a pynq equivalent for Altera . Great stream !

That's just so impressive

I am using a ZCU216 board, I am able to follow the steps until the hardware is programmed. I am using SFP cage transceivers to create a loop back test. The issue is when I try and do program device and load the bitstream nothing comes up. I only see the SysMon and nothing from the IBERT. Am I missing something? Also I selected the internal clock.

I am learning from you in few videos more than whole my bachelor and master. Big thank you

its very old, but i have one use it for video frame buffering for my hardware encoding and decoding

Hello Andrew, Thank you so much for this valuable information. I just have a question. You always mention and showing your designs in vivado during streaming but you never say any reference for them. Is there any chance that we can access them for learning purposes? Specially the one with PCIe, DDR and Microblaze. Thank you in advacnce

Just best stream ever. Big thank you for your time

That's a gigantic AXI 😂

Can you put like 16-32GB RAM into that SODIMM then load big LLM model into this ZCu104 ?

Mind uploading the design files to GH so we could understand what's going on a bit better? Because you're familiar with your code, you go through it quite fast, too fast. I also have a Zuboard (no m.2 adapter, though), so I'm also curious about how you've set it up for this test. I'd love to experiment with PCIe on both Xilinx and Altera platforms, but sadly my other FPGA is a DE10-std so that's not happening until an affordable Agilex 3/5 comes out

I was totally excited to sit down and watch this walk-through as I am beginning to test the waters of a FPGA design. But FPGA Zell it appears to give us a video of him talking to himself in front of a camera. We are unable to read your thoughts so as you mouse around the screen making comments we are lost to what is going on in your head and what you are doing. I hope your future videos will have more of a explanation to what you are thinking as you look around the GUI.

Hello, first of all, thank you for your video, I would like to ask you a question. How can I find out how uBlaze-V kernel compares to regular uBlaze?

Why not demo in ZYNQ or Artix-7 based FPGA, since VERSAL is EE edition only, with 3,000$ license.

Your streams are so incredibly helpful even a couple years later… it’s too late now but any chance for future ones with better resolution then 720 ? Zooming in on text can be tough at 720

Thanks a lot man!

I am searching open-source RISC-V IP can fit it into AMD (soft-core) like microblaze, can you please prupose some link resources for that, or if you can live session , Thank you

Thanks for your amazing contents. They are pretty helpful. Just how can i notify about your live sessions?

Any chance of you getting a SoC and have the two sides (Nios V and ARM) talk with each other, and do whatever? It can be something simple, although you could slap on an SD a pre-built Linux image, if one exists for whatever board you got. Maybe even just run two identical codes simultaneously, and have one side signal to the other that it's done and compare the run times (maybe also include the time it takes to signal?) of the two. CycloneVs are cool. Waiting for cheap/educational Agilex devices to come out

Hi Pynq lora please

@FPGA_Zealot please send the Github link of above project

I was hoping for like a Resnet-50 benchmark. any chance you know where i could find that?

Thanks a lot for this stream ! I learned a lot of techniques which I never knew before !

What is your Linux machine configuration, like RAM and #CPUs?

I may have missed that part but why do you wanna do microblaze if you have hard zynq us+ ?

How much is it?

Thanks a lot for these live streams! Super helpful. I was getting the same error as you near the end even after pointing the launch.json to the BOOT.bin. After hours of head scratching, I realized I'd forgotten to enable access to the axi interrupt controller in the platform setup tab of Vivado. Keep up the great streams mate :)

Wonderful topic. Would you be interested to talk more on versal potential applications in space?

this board is so great!, can you help me how to buy it? thanks for your video

Good talk on pcie on xilinx/amd

Nice yo

Very interested in the VE2302, this is most appreciated. Thanks for your efforts and to the group that donated it!

Thank you for being willing to make such detailed videos for such a niche subject. Every video I see uploaded by you catches my attention.

thanks so much, great video!

Is there a guide to run Linux on this board?

Did you ever figure out how to get RWEverything to access the memory addressed by your BAR?

Is it possible to do this on Xilinx Alveo U280 cards?

Real bad presentation skills. It might be better if it was done offline and edited, than in a live stream!

Hi bro, can you please make the video for testing performance in this project or any related PCIE project ?

keyboard name please

It sucks that they still sell these but havent updated anything to keep up with the open source tool chains. The make file is useless, at least on windows. Had to make a batch file that runs the commands automatically to generate the bitstream with the bootloader header. The ecp command failed because of the --compress flag is no longer valid. Nextnpr says there is no clock signal. So the program never runs, bootloader does, but nothing after. And to make things worse, i found out i dont even need a FPGA as there are apparently dedicated FIFO ICs. Might as well have just burned 100 dollars haha.