Відео

Camera man needs a pay cut immediately

What font are you using in your Terminal?

Ubuntu probably has a headless java installed Interesting, it seems University of Quebec has continued developing RARS, they made a 1.7 version at rarsm/rars

You'll probably write assembly that one time when you have a critical piece of code, and the compiler is doing something absolutely funky / refuses to optimise, and you spend 2 days figuring out just the right instructions... but in the end your hot loop now runs 30x faster

This is great! Thank you.

do we have a course website?

47:41 C++ can do `int a, b, c;`.

Awesome yt channel, ur videos are easy to understand and flow .. well presentation and clear explanation keep upload sir...

Great class

Sweet

Hi Jason, I really want a JTAG test device, e.g. SN74BCT8373, but unfortunately not really available, especially not in DIP packaging. Do you have experience with this or something similar or could you recommend something that I could use while developing a JTAG host program? Br. Gábor. Greetings from Hungary.

Thanks for this Lecture. From Jakarta Indonesia

A rather useful overview of the RISC-V register architecture and assembly instructions / quirks, thank you. Old: Z80 / 6502 dude

Excellent Jason - thank you

excellent thank you

I really found this helpful Jason, thank you

22:58 that was a good blooper haha

Thank you very much 🙏 🌷

@6:33 Correction: slli rd, rs1, immediate # R[rd] = R[rs1] << immediate srai rd, rs1, immediate # R[rd] = (signed)R[rs1] >> immediate srli rd, rs1, immediate # R[rd] = (unsigned)R[rs1] >> immediate @6:57 Correction: add: bne rs1, rs2, offset # if (R[rs1]!=R[rs2]) PC += sext(offset) modify: jalr rd, offset(rs1) # t=PC+4; PC += (R[rs1]+sext(offset)&~1); R[rd] = t

I love you daddy

Yass daddy

Go daddy!

@13:22 I have some sloppy coding for the calculcation of the JALR target. Remember that our RISC-V CPU is word address (as decision I regret in hindsight). The original code was shown as: assign jalr_offset = instruction_EX[31:20]; assign jalr_addr = readdata1_EX[11:0] + jalr_offset[11:2]; There are two issues with this code. (1) The second line adds a 12 bit value to a 10-bit value, which leaves the decision of whether to sign extend the second operand to the compiler. I'm not sure if Modelsim/Verilator would sign extend or zero-extend the second operand, but I think that unless you declared jalr_offset as: logic signed [11:0] jalr_offset; ...I assume it will treat this signal as unsigned and zero-extend in the addition. (2) The address stored in R[rs1] is a byte address and should be converted to a word address. The proper code should therefore be: assign jalr_offset = instruction_EX[31:20]; assign jalr_addr = (readdata1_EX[13:2] + {2{jalr_offset[11]}},jalr_offset[11:2]}; I'm sorry for the confusion.

Corrections: @5:28 I meant to say "shift right logical *immediate*". @22:32 While the assembler does expand the nop instruction to the addi x0,x0,0 instruction, the 0x00000000 machine instruction doesn't map to addi x0,x0,0 instruction.

Correction: at @28:13 slide header should be "Comparator" not "Shifter"

@00:08 "synchronous" is mispelled on the list of topics! Sorry!

I'm sorry for the strange letterboxing on this video. Somehow, the video size was set to a nonstandard aspect ratio, causing the letterboxing. I'm sorry I missed this prior to posting.

which software for system verilog

@2:27 Correction: That should be 100 nanojoules per flop for the 328p, so it's only 2000 times less efficient than Summit.