Відео

Why is your pmos 7.2 and your nmos is smaller?

Unspecified I/O Standard: 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a, b, and y. i am getting this as error. how to solve this

Why have you used metals to interconnect the transistors when you could overlap the drain and sources of the pmos and nmos in cascode?

Where did you get cadence from?

Please re-record and upload!

I get the output with three quantized levels, I tried the same circuit using symbols (to make the circuit look beautiful)

Where enger3426 file

stop uploading these type of time waste videos..waste of time

sir,can u please help with the restoring of design

19:00 via connect poly with metal1

can you show us physical design of adder and subtractor

Please do proper recording,all main steps are not recorded here

Thank you very much.

No sound no effective

Sir, whatever your explaining with audio was different from video so please clarify it sir

Dear Sir, sorry to says that i am unable to understand how to giving virtual input and outputs so can you please explain slowly with one more video

If I want to add some plain text in schematic widow, then how can I do that ? Kindly answer.

helpful! what is the channel length of the transistors you have used in your design ?

Great work sir Really helpful :)

Thank you, very good video

It is like seeing movie in unknown language

Dear sir, Please tell me how to set PIN numbers in the IO planning for genesis 2 I am unable to get it as I am an initiator and from Computer science background

How can I install Cadence tools such as virtuoso 6.1.8, Incisive with license ?

you saved me ..thank u so much.. i was thinking about why object windows is empty

Sir, Can you please tell me how to check which technology report it gives after synthesis, 45nm, 90nm or 180nm

Very nice explanation. Thank you

"iCarus" is pronounced with a soft I sound. It is not "eye-car-us" it's "ick-ar-us".

How can i select edge partial ?? i pressed f4 as u said but nothing happens.

Vedio on how to find area and speed on vivado?

How to insert a cell instance in Glade

Amazing Simulation, This really helps in learning HDL and for checking the results in simulation. The best thing is how easy it is to simulate the code and configure the input ports.

Could conduct work shops for students???

how to plot vin vs vout to get hysteresis chart?

Due to COVID19 Pandemic colleges are not opening and I can't access the cadence software so I searched for an open source software and I found GLADE. Check out my playlist on Layout Designing using GLADE. #LearnFromHome Playlist Link:- ua-cam.com/play/PLWcG9vtrFH0YVZvd3yf2Xmm_Gl0y-XXz6.html Video 2&3: Glade Downloading, Setup and Configuration. Video 2 link: ua-cam.com/video/LMZ3O6Akfro/v-deo.html Video 3 link: ua-cam.com/video/1ueSinMmqkA/v-deo.html Video 4: Designing Layout of nMOS and pMOS is explained. Video 4 link: ua-cam.com/video/oOblwp65WFA/v-deo.html Video 5: Designing CMOS Inverter Layout using 1 metal layer is explained in detail. Video 5 link: ua-cam.com/video/Qr0nTPo-Ri0/v-deo.html Video 6: Verification of Designed Inverter Layout using LT Spice. Video 6 link: ua-cam.com/video/kvrF6Zv6Y_U/v-deo.html Video 7: Designing CMOS Inverter Layout by using 2 metal layers and Vias. Video 7 link: ua-cam.com/video/HZopqROB2GA/v-deo.html Video 8: Designing 2 Input CMOS NAND Gate. Video 8 link: ua-cam.com/video/41067AYX_do/v-deo.html Video 9: Verification of Designed NAND Gate Layout using LT Spice. Video 9 link: ua-cam.com/video/3pufZ6InuHQ/v-deo.html Video 10: Designing 2 Input CMOS NOR Gate. Video 10 link: ua-cam.com/video/skYC2UnJgQ4/v-deo.html Kindly Like, Share among your engineering friends so that they can also learn from home and subscribe to my Channel for more GLADE Tutorials. Your Support will be appreciated. Thank You

Due to COVID19 Pandemic colleges are not opening and I can't access the cadence software so I searched for an open source software and I found GLADE. Check out my playlist on Layout Designing using GLADE. #LearnFromHome Playlist Link:- ua-cam.com/play/PLWcG9vtrFH0YVZvd3yf2Xmm_Gl0y-XXz6.html Video 1: All the CMOS Design Rules are explained. Video 1 link: ua-cam.com/video/b3IlK1WZIHA/v-deo.html Video 2&3: Glade Downloading, Setup and Configuration. Video 2 link: ua-cam.com/video/LMZ3O6Akfro/v-deo.html Video 3 link: ua-cam.com/video/1ueSinMmqkA/v-deo.html Video 4: Designing Layout of nMOS and pMOS is explained. Video 4 link: ua-cam.com/video/oOblwp65WFA/v-deo.html Video 5: Designing CMOS Inverter Layout using 1 metal layer is explained in detail. Video 5 link: ua-cam.com/video/Qr0nTPo-Ri0/v-deo.html Video 6: Verification of Designed Inverter Layout using LT Spice. Video 6 link: ua-cam.com/video/kvrF6Zv6Y_U/v-deo.html Video 7: Designing CMOS Inverter Layout by using 2 metal layers and Vias. Video 7 link: ua-cam.com/video/HZopqROB2GA/v-deo.html Video 8: Designing 2 Input CMOS NAND Gate. Video 8 link: ua-cam.com/video/41067AYX_do/v-deo.html Video 9: Verification of Designed NAND Gate Layout using LT Spice. Video 9 link: ua-cam.com/video/3pufZ6InuHQ/v-deo.html Video 10: Designing 2 Input CMOS NOR Gate. Video 10 link: ua-cam.com/video/skYC2UnJgQ4/v-deo.html Kindly Like, Share among your engineering friends so that they can also learn from home and subscribe to my Channel for more GLADE Tutorials. Your Support will be appreciated. Thank You

Sir can you tell me how can i find out the .tch file

Part-2 Video ua-cam.com/video/o5U4_7KKRhw/v-deo.html

Thanks it helped me a lot:)

Helpful video 👍 please upload memory files too

nice content

Can someone tell me if this comparator could work on S-D modulator?

Is this a behavioural simulation? How can I do a post-route simulation? TY

Your circuit is good. And please tell buy a video that how we find the value of any circuit in cadence...... Please.... 👍👍👍👍

can i overlap both pmos source ? will it work?

Beautiful I love you

Very helpful Go to heaven and what not

Dear Sir I am pursuing a PhD in VLSI Design (Topic Design of Low power Dickson charge pump using inductor Technique ), working on Cadence Virtuoso Tools IC 616, I want to know about how to use parameter in cadence for efficiency outcome. please help in this regards .

Please tell me zener diode parameters in analoglib cadence tool

excellent work..keept it up

Thanks!