The Class D RF amplifier - Testing, testing testing... (3/3)
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- Опубліковано 8 лип 2024
- #175 In this video I conclude the discussion about the RF class D amplifier by looking at the practical implementation of the circuit I designed last time. I shortly look at the schematic and PCB design and then focus on the various tests that need to be performed just to check how well the circuit is working.
Related videos:
Class A amplifier part 1 - • The Class A amplifier ...
Class A amplifier part 2 - • The Class A amplifier ...
Class B amplifier part 1 - • The Class B amplifier ...
Class B amplifier part 2a - • The Class B amplifier ...
Class B amplifier part 2b - • The Class B amplifier ...
Class C amplifier part 1 - • The RF Class C amplifi...
Class C amplifier part 2 - • The RF Class C amplifi...
Class D audio amplifier part 1 - • The Class D audio ampl...
Class D audio amplifier part 2 - • The Class D audio ampl...
Class D audio amplifier part 3 - • The Class D audio ampl...
Class D RF amplifier part 1 - • The Class D RF amplif...
Class D RF amplifier part 2 - • The Class D RF amplifi...
Class D RF amplifier part 3 - • The Class D RF amplifi...
Used datasheets and app note:
www.onsemi.com/pdf/datasheet/...
www.analog.com/media/en/techn...
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Some observations. You can determine more accurately the output impedance of the device by putting a resistive load between the output and ½ of Vcc. Adjust the resistor until the swing is ½ of the open circuit swing. Assuming your model is accurate you might even do this in simulation. Of course, the actual device is the best for this.
Since any single device has all transistors made under almost identical processing circumstances the propagation delays and rise and fall times of each section will be much closer to a match than the data sheet numbers. It is likely close enough that the propagation delay of the circuit traces should be considered and matched. This is not much of a contributor to efficiency, as you say, but may contribute to the high frequency ringing. Some portion of the 7 ns propagation delay the complementary channels will be both partially turned on, which would contribute to inefficiency. I don't know how much that is and it may be covered by the C*V*V*f/2.
Two other factors should be considered. The traces are transmission lines. If the output impedance of a single gate were, for example, 60 Ohms you would minimize reflection at the output lead if the PWB trace was 60 Ohms. Now the square wave will propagate to the junction of the next output and the trace that continues on to the inductor. Since this is 60 Ohms from the second gate in parallel with the trace continuing on to the inductor. That is 30 Ohms. You will get a reflection that goes back toward the first buffer. Each intersection will have a reflection. The reflections often bounce back and forth between all these nodes leading to what appears on a scope as ringing on a switching edge at several hundred MHz.
It would be better to use a stripline or microstripline of the impedance of each output each the same length and then bring all 6 of them together at the inductor input node. If you have matched the input of the filter to 1/6 of the impedance of the gate output, then you will have little reflection from that node where the 6 traces converge.
The high frequency switching noise is just as likely to be ringing of the package lead inductance and the device output capacitance. The lead inductance is on the order of 1 nHy. I have seen this ringing in the 1GHz range.
It might be interesting now to use PWM to achieve modulation with your class D amplifier. If the pulses rather than having a 50% duty cycle were modulated from 0% to 50% but the same frequency you would have a kind of amplitude modulation.
I was particularly interested in this because I am making a 10 MHz frequency reference in which I’m using a VCTCXO with a 0.8 Volt clipped sine output. I feed the output through an impedance transformation circuit to be able to drive an SN74HC04 which requires > 2 Vpp input. The output then drives several other SN74HC04 sections in parallel which then feed another filter to generate a sine output to a 50 Ohm load.
Thanks to you I finally understand how my chinese class D amplifier is not broadcasting as many EMI as I thought it would, with so few filtering components.
Note that it is symmetrical, that may help.
FesZ, outstanding video. Being an EMC Engineer I see this type of problem frequently. Therefore having a simulation method helps the designers. Thank you.
Excellent work!
Thank you. These are so well done.
As always, an excellent mini series! Thanks Fesz!
Very satisfying video. Loving your RF stuff!
Thank you very much for your video, I'm watching from El Salvador
you should use a mosfet gate driver IC like the UCC27322 instead of the ganged 74ac14. That would eliminate the propagation delay overlap and give you 9 amps of drive as well. I've used one at 7.16 Mhz quite well.
It's very interesting decision. Could you please share details of your project?
Thank you for making great videos. The inductor losses could probably be further reduced with using Litz wire.
Litz loses effectiveness over solid wire above 1 mhz, and by 5 mhz the solid will win out. Litz is most effective below 500khz.
it is not easy to understand this lesson . I leaned to dig more on all types. many thanks !
Great video as allays.
Would ferrite cores help efficiency in this case or just limit the frequency ? Also what about tiny thoroids?
Also since it is a 5MHz signal is the 90 deg bend when you put inductor 2 not affecting the signal ?
Also how and why would the 2 inductors interact if they were inline?
Also on a side note where are you getting that emailed Cu wire? emag? mouser? or some hardware shop? (asking since i need a custom transformer ratio and i dont know where to go)
Superb !
Will you be going over Class E RF amps next? I am using them in my ham radio projects and would like to learn all about them in order to optimize their efficiency and maintain their reliability. I've read a couple of papers on the subject, but I learn a lot more watching your videos. Thanks.
At the moment I have some other videos in work and planned but for sure, next year I would like to cover class E and F; that's the plan anyway.
FesZ, thank you so much for these videos. One question, do you plan to cover the AB Class Amplifier as well?
Those Ferrite beads are only good for 70-150 MHz and your circuit is working at 5 MHz. They are no more than just resistors. By the way, I enjoy watching your videos. Thank you.
While the amp "works" it is important to observe FCC rules on harmonics before placing it on the air.
That is a very good point that is in general valid for any RF amplifier. However, I never intended to use this circuit "on the air", it was built as a demonstration to highlight the operation and method of design. As you mentioned, FFC rules on harmonics, or the equivalent in any other country is important to consider - that is why I specifically measured this. May I ask what sort of ratio is mandatory between fundamental and the next harmonic in your region?
@@FesZElectronics Here in the USA the harmonics must be 50db down from the fundamental. Difficult to meet with a class D amp and have any advantage over a class C.
Surprisingly good result, quite usable for some low-power FSK or PSK.
I’d try to modify the simulator’s parameters with parallel capacitances to the inductors to see if that gives you your ringing. Because if you can predict that behaviour when designing a switching circuit based off datasheet parameters, it would be rather useful. Not sure how I’d measure capacitance though. A current-mode resonant driver?
Hello James! Regarding measurement of capacitance, one technique used in SMPS design is to measure the exact frequency of ringing, and then add more capacitance and observe how the frequency changes. Based on the deltaF and deltaC the initial capacitance can be worked out.
Since the initial capacitance has to do both with the components and the layout, I think the best approach is just to leave some component place holders in the design, and finetune the values on the practical board, rather than rely on simulations alone.
I'm wondering what te impact of probing is in the ringing, that may also easily add a few pF
A direct probing will indeed affect the frequency. That needs to be accounted for if you are interested in measuring the circuit capacitance. When I measured the circuit, in the oscilloscope (with probe ~16pF) measurement I was getting ~230MHz, but in the spectrum analyzer measurement (without the probe) the spike appeared at ~360MHz.
Many thanks for the video. I have several questions / observations. (1) Shouldn't the efficiency of a class D PA actually be determined by measuring AC current on HF frequencies? I don't think that a typical DMM is a proper instrument for doing this (especially in a DC current mode). This will probably require a home build current probe. (2) How one can measure (not model) an output impedance of a class D PA? Is it even defined considering the fact that half of the cycle there is literally no current on the output?
Regarding the first point, in-between the power supply and the actual amplifier, I did add some filtration and decoupling. So I was not measuring the current being drawn by the switching stage, that current is coming from the local capacitors, but rather I was measuring the current needed to constantly replenish the capacitors. Honestly I did not check how much ripple there is on the supply line, but considering the large capacitors and ferrite on the board (100nF+2.2uF ceramic and 470uF electrolytic) I will assume minor AC component is left in the supply current.
For the second point, I'm not sure I understand; you always have both current and voltage on the output (if by output you mean the resistive load); if you are referring to the push pull switch as output, then you still have current even when this is at a low voltage, since the current is coming from the LC part of the RLC circuit. When the high side switch is on, you don't just supply the "R", you also charge up the LC, and when the low side switch is on, you simply close the series RLC circuit, to form a loop trough ground. Current is always oscillating trough the RLC circuit.
@@FesZElectronics (1) This is actually a good point, thanks! (2) Yes, I was curious specifically about the switching part of the circuit, (!) before any L/C components. Is my understanding correct that if we consider only this part we can't talk about any particular output impedance?
I'm not sure on the exact technical definition, but if you are not considering the "LC" part, its not really a class D amplifier, its just a half bridge (for the voltage switching circuit I showed in this video). What you connect after it determines what kind of circuit it is - for example with a series inductor, and then a parallel capacitor and resistor, its a buck converter... Strictly referring to the switches, we can work out an "output" impedance - the impedance into which maximum power can be delivered - which is equal to the switches resistance. However, to maximize efficiency, the resistance in the RLC circuit usually is of higher value.
Can you make a video about management of return currents flow relative to their source?
Very interesting, thanks. Did you consider adding a push pull transistor output pair on a higher HT for some useful RF power?
Can you make video about 88-108MHz FM receiver? Real signal parameters, amplitude, frequency spectrum, simple mixing on diodes for example and decoding with pll…
To help beginners to understand and build few transistors FM radio?
Fantastic! Your explanations are very clear and thank you for this video 👏🙂👍A few comments if I may.
At 17:02 you say a snubber circuit can be introduced to prevent the switching spikes + ringing noise is the first place.
1- Question, In your experience, which circuit is most effective to produce the cleanest sine wave from Class D, snubber circuit or output filter (as you show in the video)?
2- Question, to improve efficiency…is it possible to use a snubber circuit only (high efficiency), and avoid using output filter (low efficiency)? The inductors and capacitors in output filter seem to waste lots of energy as heat.
3- Suggestion, in future video can you show how LTSpice can simulate snubber circuit, to determine optimal component values for -30dBc or better? I imagine a snubber circuit would add RC components connected between gate and drain of FET to provide negative feedback (maybe side effect = lower amplifier gain but I am not sure)
I mention these 3 points because a very clean RF output is required by government…depending on frequency and country (examples: Germany -40dBc, US -43dBc, ITC -50dBC or more).
It would be good learn how such clean RF outputs can be achieved while maintaining high efficiency.
You are a wonderful teacher and it would be good to learn more about how to design the noise control circuits for FET amplifiers. 👍
I think the answer to all 3 questions is related - you will need an output filter for a class D amplifier - this is needed to filter the square wave into a sine wave. It is not uncommon for practical amplifiers to have multiple stages of filters (in my design I used a single T filter, but you can have 2 to 4 T filters cascaded); this is needed to pass the output signal cleanliness requirement. How lossy the filter is has to do with the used components, perfect filters don't exist.. Anyway, a real amplifier will never be ideal, so its perfectly normal to have losses.
The snubber and ringing are a different problem - these are related to unwanted parasitics in the switching stage. You can either rely on the output filter or build a snubber to reduce the noise reaching the output, but as another viewer correctly pointed out, the ringing can generate voltages high enough to destroy the switching transistors, so if the problem is that severe, the snubber will be mandatory.
I do plan to cover snubbers at some point in the future, not sure when though.
@@FesZElectronics Thank you for the detailed and clear explanation 👍mulțumesc!! 🙂 RF content on your channel is A++++, better than so many other RF channels on YT in my opinion - I am recommending FesZ Electronics channel to all my RF colleagues at work. For snubber circuits, I have searched for many years to find literature or technical reference that shows the exact purpose and behavior of a snubber circuit for FET push-pull amplifiers, but unfortunately...most information from others is not clear or not scientific, maybe magic or top secret. So I am very happy to hear you plan to cover snubbers at some point in the future in your videos. It is common to see FET PA's with 4 different types of 'noise control' circuits: 1) drain-to-gate negative feedback, also called snubbers, 2) drain-to-ground C, LC or RLC compensation, 3) drain-to-drain C, LC, or RLC compensation, and 4) output filters such as Lowpass, or Bandpass. Output filters (type 4) are easy to understand. However noise control circuits Type 1 (snubbers), Type 2, and Type 3 are not easy for me to understand, so I hope to learn more in future especially with LTSpice or other simulations. Thank you again Fesz for sharing your videos and great work, Bravo!!
Thank you for the kind words and the detailed explanation of various countermeasures in your experience! I personally, mainly came across snubbers (drain to source RC) in power converters - this is the type 2 you mentioned; from an operating point of view, it should be the same in PA or SMPS. As documentation support I highly recommend: fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/buck_snubber_app-e.pdf
Type 1 sounds like it would reduce noise by increasing the switching time - larger slope means less high frequency harmonics, but also more inefficient. For switching converters, this sort of noise countermeasure is implemented by a larger or smaller gate resistor; maybe even some diodes to control turn on and off at different rates.
Hi FesZ Electronics! I was just watching your "A spooky circuit - The Theremin" video and I am going to try to make one. I printed out your schematic for it but I cant seem to find the values for some of the capacitors. Specifically C2 in the volume oscillator, C23 in the pitch oscillator variable, C15 in the pitch reference oscillator, and C19 as the power smoothing capacitor. Do you happen to still have it or do you have the values somewhere? If you don't, do you have a guess as to what these could be? Sorry for posting here but I don't know if you will respond to a comment on a video you made 3 years ago.
Hello, the values are not that important there, anything in the 10-100uF will do.
Very good presentation.
Can you please check operation at 6V? (Still below absolute maximum so won't cause damage to the IC)
The only difference that should occur is that the output voltage becomes larger. The equivalent resistance of the power stage should be more or less the same, however parallel capacitance related losses should increase since those are voltage dependent.
@@FesZElectronics I asked because CMOS transistor/switch resistance is getting lower with voltage increase.
You can see that on analog mux resistance and on FASTER OPERATION if 74 logic with voltage increase from 3V to 5V.
Please show us if it's not too complicated to you.
Careful with getting close to the max ratings here, the ringing should probably also stay below the max level so it's not just the supply to keep an eye on
@@FesZElectronics
Please, at the worst case a poor hex inverter IC will give his life on behalf of the science.
Can I use this to boost my mobile network
It's important to realise that this is NOT a Class-D amplifier, but Class-C. In Class D, the wanted signal is dictated by the PWM of the switching "carrier", but here you are amplifying the carrier itself. The efficiency is of a similar order. Also, given real component tolerances, adding the 10pF across the 1 nF is pointless - the 1nF will already have a much wider tolerance that swamps the 10pF (as well as strays on the PCB, etc). Instead you need to use adjustable capacitors (or inductors) so that the network can be tuned to the exact value to give maximum power output at the frequency of the carrier. I think this series is generally pretty good, but you are inadvertently spreading misinformation about what Class-D is, as well as a small misrepresentation of practical design techniques.
I think it's a class D because the output transistors are working in cutoff and saturation without going through the active zone.
No, PWM is just one possible way of driving Class D amplifiers. You can also drive a class d amp with sigma delta modulation, for instance. It is the mode in which the transistors operate that determines the class of an amplifier.
This is Class D. It's the conduction angle of the transistor. In Class D, transistors are exclusively used as switches and not as linear gain devices. This design definitely satisfies this criteria.
@@m1geo Well, if you are strictly going by conduction angle, each transistor is on for 50% of the time, or 180°. That makes it Class-B. Also, really a 3rd harmonic of -35dB isn't that impressive. For a RF transmitter, that would generally have to be >65dB down.
@@GRAHAMAUS In class B or AB each transistor is in the active zone for 180°, not in saturation. In this case each transistor is in saturation, not active zone for 180°.