FIFO Complete Verilog Code with Explanation | First in First Out | VLSI POINT
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- Опубліковано 30 лис 2024
- In this video, I have discussed the complete verilog code of FIFO(First In First Out). FIFO is very important for exams and interviews. This is the 3rd video of "FIFO in English" playlist. This playlist consists FIFO basics followed by FIFO depth calculation questions and FIFO Verilog code.
Following topics are covered in this Playlist:
What is FIFO?
Why do we need FIFO?
FIFO applications
FIFO depth calculation
FIFO verilog code with explanation
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Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar
#FIFO #fifo_depth_calculation #first_in_first_out
Very useful series. Please also make videos on communication protocols like SPI, UART etc.
Mam also make videos on protocols,spi,i2c,uart, gpio etc...
Nice presentation. Can u make a seperate video on asynchronous fifo?
Hello, the video was very helpful! I have a doubt regarding the line: memory
Ma'am very useful verilog series...can you please make it series on system verilog?
this is a synchronous fifo right with asyn reset?
Mam for reading part you write one condition that if( write _en && (write_ptr==rd_ptr))
Then full_reg
yeah same doubt
Mam could you please make vedio on 8x16 asynchronous dual Port ram
Hi mam, I want to learn MagCAD tool and CMOS VLSI design BIST. Any possible? Please guide me
Voice over slide approch is poor one in explaining the complex topic, it makes tutorial less engaging however it might seem cool. Marker board approach is good for complex topic explanation.
Why you take PTR as 5 for 16*8 depth fifo
for overflow condition
@@vlsipoint can you elaborate for better understanding about fifo oberflow
Thank u mam❤😍
Is this sync FIFO or async FIFO VERILOG code
Async FIFO, since we have @(posedge clk or posedge rst). For sync it'll be only posedge clk and then in the process we'll check reset.
Ma'am, Here why u have taken PTR_ SIZE = 5 , why not 4 , since parameter DEPTH is 16
exactly if PTR_SIZE=5 THEN AFTER depth extra 5 locations will be present so i think its mistake .if i said wrong any one tell me
You need one extra bit in the pointer to detect the wrap around condition, particularly to detect FULL condition.
explanation is poor
Can i know Ur from design or verification ?
I had worked in Verification at NXP Semiconductors
Plz send test bench
ASYNCHROUNCE FIFO