A board was designed, and the new version of the amp was tested. After some tweaks it seems to work. Part 1: • #139 - Agilent 33250A ... Datasheet: www.ti.com/lit/ds/symlink/ths...
Great video as usual. No professional advice here, just amateur suggestions. If the problem is input to output coupling, I would relocate the amplifier to the output side of the board to minimise the length of the radiating track. I'd also use an unbroken ground plane under the input and stitch the ground down. From what I've read it's generally better to retain unbroken grounds unless the RF/EM simulations tell you otherwise. I realise I'm contradicting the datasheet here, but a nearly split ground plane next to a high power RF output track just seems problematic. Thanks again for the great technical content!
Hi freq stuff.....a black art! Having two copper pours, one on each side of the board and one being broken also i suspect is a problem......if i read your design properly. Try getting rid of all the copper pours, dont cross traces top and bottom, or if you do then at right angles only. You might get away with a bottom side unbroken pour for gnd, but to experiment I would make both designs at same time so you can swap out. Keep traces away from other unrelated pins when you run past them. Use vias to drop down to the ground pour, but as close to the topside pad as possible.
Nice to see you post! love your videos. Please can you make a Simple DIY ESR meter incircuit ? maybe with 7Seg display. I live in a country where The chinese ESR meters are worth as much as a whole month salary
Can someone explain a couple of things please: 1) why the rails of opamp are taken from pins 18; 19 and 1; 25? It appears to be a part of the overcurrent protection with external shunts in series with the bipolar push pull output stage. The remaining hybrid circuits are powered by 13;16 and 7;3. Wouldn't a composite amplifier be more appropriate here? And a shell load below 50 ohms still causes a bouncing output even without those decoupling caps and potentially rendering this OCP useless? The datasheet emphasizes on using 2 in parallel. 2) Why use these physically large capacitors? The size is like 1206. Could this be a parasitic RLC adding instability? Is that what they call self-resonance? Is 0402 next to the power rail pin more suitable?
if I were you , I didn't use FR4 material , parasitic capacitance and inductance is high ,I also don't use ground plane unless if you know what you are doing , neither via , via has inductance too.
I've found parasitic capacitance on the output pin to cause this kind of thing in the past. Perhaps a few ohms in series with the output physically sited as close to the output pin might be enough to reduce the (admittedly low) capacitive loading on the output trace/off module traces without compromising calibration range?
This is one of the worst f-gens on the market. Used to have two of them in the lab. First of all atenuator was quite leaky, also output off function was not the real output off, and to add insult to injury manufacturer tehnical support was telling me it is ok, that is the way it was intended to operate like that. After about two years of use one of the instruments started to show extreme dropp-off in amplitude over about a 1 or 2 MHz frequency. Since warranty passed, i opened it just to find ferrite transformer secondary on the output of the amplifier not properly soldered to ground. (It looks like ferrite bead with two leads forming primary and secondary. Signal from the amp goes through one lead and the other is forming short circuited turn connected to ground.) I repaired it, and next day i put my 33250s on the ebay and lowred the price just to get rid of them. Simply piece of s***t of a generator.
@@feedback-loop Oh, that is a large question, but I'll try. Just remember I am nowhere near as skilled as you, I do only know about layering, frequency and a bit about EMI on boards. Your signal layer looks fine, but your solid copper layer is maybe the reason for all your problems. :-) Each time you have a cutout in that layer do, you create an artificial barrier for your signal layer, and this will most of the time force your signal in the signal layer to make a detour through the board. This can give a lot of reflections, crosstalk and delays. The best is to never ever make any dent, cut or paths in a ground layer. EDIT: You have to remember that a signal does not run through the tracks, but in the boards material.
@@friedmule5403 I believe I showed the "layout" section of the datasheet in my previous video. it says, in particular, "Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board."
@@feedback-loop Yes, that is right, but I am fairly sure they mean planes on the same layer. A normal rule is to never get below 20H meaning planes on the same layer must not get closer than 20 x the High between this layer and the layer next to. It may not be intuitive, but the problem gets bigger the lower the frequency, and you are almost running DC, compared to the GHz that is normally used in high speed layout. If you look at the suggested layout is there a lot of vias in the layout and all these goes to an uninterrupted layer below. As stated before, am I no expert, but this looks like a typical impedance problem with reflecting EMI. :-)
@@friedmule5403 Did you look into the datasheet? In particular, layout example and Figure 10-13. Ground Trace Cutout Beneath the Device Inputs and Output
Great video as usual. No professional advice here, just amateur suggestions.
If the problem is input to output coupling, I would relocate the amplifier to the output side of the board to minimise the length of the radiating track. I'd also use an unbroken ground plane under the input and stitch the ground down. From what I've read it's generally better to retain unbroken grounds unless the RF/EM simulations tell you otherwise. I realise I'm contradicting the datasheet here, but a nearly split ground plane next to a high power RF output track just seems problematic.
Thanks again for the great technical content!
Thank you for sharing, you should know your videos are really appreciated no matter what you work on, a microphone, a speakwe or test equipment.
Thank you.
Thank you very much!
Hi freq stuff.....a black art!
Having two copper pours, one on each side of the board and one being broken also i suspect is a problem......if i read your design properly.
Try getting rid of all the copper pours, dont cross traces top and bottom, or if you do then at right angles only.
You might get away with a bottom side unbroken pour for gnd, but to experiment I would make both designs at same time so you can swap out.
Keep traces away from other unrelated pins when you run past them.
Use vias to drop down to the ground pour, but as close to the topside pad as possible.
Awesome...cheers.
Very interesting.
Nice to see you post!
love your videos.
Please can you make a Simple DIY ESR meter incircuit ? maybe with 7Seg display.
I live in a country where The chinese ESR meters are worth as much as a whole month salary
Can someone explain a couple of things please:
1) why the rails of opamp are taken from pins 18; 19 and 1; 25? It appears to be a part of the overcurrent protection with external shunts in series with the bipolar push pull output stage. The remaining hybrid circuits are powered by 13;16 and 7;3. Wouldn't a composite amplifier be more appropriate here? And a shell load below 50 ohms still causes a bouncing output even without those decoupling caps and potentially rendering this OCP useless?
The datasheet emphasizes on using 2 in parallel.
2) Why use these physically large capacitors? The size is like 1206. Could this be a parasitic RLC adding instability? Is that what they call self-resonance? Is 0402 next to the power rail pin more suitable?
if I were you , I didn't use FR4 material , parasitic capacitance and inductance is high ,I also don't use ground plane unless if you know what you are doing , neither via , via has inductance too.
I've found parasitic capacitance on the output pin to cause this kind of thing in the past. Perhaps a few ohms in series with the output physically sited as close to the output pin might be enough to reduce the (admittedly low) capacitive loading on the output trace/off module traces without compromising calibration range?
This is one of the worst f-gens on the market. Used to have two of them in the lab. First of all atenuator was quite leaky, also output off function was not the real output off, and to add insult to injury manufacturer tehnical support was telling me it is ok, that is the way it was intended to operate like that. After about two years of use one of the instruments started to show extreme dropp-off in amplitude over about a 1 or 2 MHz frequency. Since warranty passed, i opened it just to find ferrite transformer secondary on the output of the amplifier not properly soldered to ground. (It looks like ferrite bead with two leads forming primary and secondary. Signal from the amp goes through one lead and the other is forming short circuited turn connected to ground.)
I repaired it, and next day i put my 33250s on the ebay and lowred the price just to get rid of them. Simply piece of s***t of a generator.
I think your main problem is your layering and ground design. I think your board may have some EMI problems and problems with its impedance.
What would you change?
@@feedback-loop Oh, that is a large question, but I'll try. Just remember I am nowhere near as skilled as you, I do only know about layering, frequency and a bit about EMI on boards.
Your signal layer looks fine, but your solid copper layer is maybe the reason for all your problems. :-)
Each time you have a cutout in that layer do, you create an artificial barrier for your signal layer, and this will most of the time force your signal in the signal layer to make a detour through the board. This can give a lot of reflections, crosstalk and delays.
The best is to never ever make any dent, cut or paths in a ground layer.
EDIT: You have to remember that a signal does not run through the tracks, but in the boards material.
@@friedmule5403 I believe I showed the "layout" section of the datasheet in my previous video. it says, in particular, "Parasitic capacitance on the
output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board."
@@feedback-loop Yes, that is right, but I am fairly sure they mean planes on the same layer. A normal rule is to never get below 20H meaning planes on the same layer must not get closer than 20 x the High between this layer and the layer next to.
It may not be intuitive, but the problem gets bigger the lower the frequency, and you are almost running DC, compared to the GHz that is normally used in high speed layout.
If you look at the suggested layout is there a lot of vias in the layout and all these goes to an uninterrupted layer below. As stated before, am I no expert, but this looks like a typical impedance problem with reflecting EMI. :-)
@@friedmule5403 Did you look into the datasheet? In particular, layout example and Figure 10-13. Ground Trace Cutout Beneath the Device Inputs and Output